Programmable DMA Controller Bus Priority Management
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Solution Overview
Problem
Conventional direct memory access (DMA) controllers in microprocessor systems have limited flexibility due to their priority over the central processing unit (CPU) when accessing the shared memory bus, which can stall the CPU and restrict system performance, especially in scenarios requiring low-power modes and asynchronous event handling.
Innovation Solution
A programmable DMA controller system that allows for priority modes, independent operation from the CPU, and the ability to suspend or resume DMA channels based on control signals, enabling the CPU to enter power-saving modes while the DMA controller handles asynchronous events, and allowing only necessary components to be activated during transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DMA controller has priority over the CPU when accessing the shared memory bus, then the DMA transfer speed and efficiency are improved, but the CPU may be stalled and system flexibility is reduced
Solution Approach 1:
The patent implements dynamic priority assignment where the DMA controller's bus priority is not fixed but can be adjusted based on system conditions. The CPU can temporarily suspend DMA channels when it needs bus access, and the DMA controller can resume channels when the CPU releases the bus. This dynamic adjustment resolves the contradiction by allowing high DMA priority during transfers while maintaining CPU flexibility when needed.
2Productivity
If the DMA controller operates independently from the CPU, then the CPU can perform other functions and productivity is improved, but power management flexibility is reduced
Solution Approach 1:
The patent enables dynamic control of DMA operation modes where the DMA controller can be suspended or resumed based on power management requirements. When the system enters low-power mode, the CPU can suspend DMA channels to save power while maintaining the capability to resume them when needed. This resolves the contradiction by allowing independent DMA operation for productivity while adding power management flexibility through suspend/resume capability.
Solution Approach 2:
The patent changes the operational parameters of the DMA controller by introducing suspend and resume states. The DMA controller can transition between active, suspended, and resumed states based on system requirements. This parameter change allows the system to balance between independent operation (for productivity) and power management flexibility by adjusting the DMA's operational state.
3Reliability
If the CPU is prohibited from accessing the memory bus during DMA transfer, then bus collision is prevented and DMA reliability is improved, but system adaptability is reduced
Solution Approach 1:
The patent implements dynamic bus access control where the prohibition of CPU access during DMA transfer is not absolute but conditional. The CPU can request bus access by suspending DMA channels, and the DMA controller can grant temporary bus access while maintaining transfer reliability through proper state management. This resolves the contradiction by making bus access rules dynamic rather than static, allowing both reliability and adaptability.
Data Source
AI summary
A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.