Programmable Logic Device Configuration via DMA Bus Interface
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Solution Overview
Problem
The increasing size of configuration data for programmable logic devices (PLDs) leads to longer configuration times, which can be problematic in situations where quick availability is desired, such as during power-up or in high-speed applications.
Innovation Solution
The configuration data is split into two stages, with the first stage loaded quickly to establish a bus interface module and internal configuration access interface, and the second stage loaded using direct memory access (DMA) transfers to reduce CPU utilization and speed up the configuration process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If configuration data is loaded using traditional memory interface, then device can be configured, but configuration time increases as data size increases
Solution Approach 1:
The configuration data is divided into two distinct stages: first stage configuration data that establishes basic device functionality and interface circuits, and second stage configuration data that programs the programmable logic. This segmentation allows the device to become operational with minimal configuration data while the remaining data is loaded asynchronously, thereby reducing the critical configuration time while accommodating large total data sizes.
Solution Approach 2:
The first stage configuration data is loaded and processed in advance to establish the bus interface module, storage interface circuit, and internal configuration access interface before the second stage configuration data loading begins. This preliminary action creates the necessary infrastructure for high-speed data transfer and enables the device to meet time-to-availability requirements independent of the total configuration data size.
2Loss of time
If configuration data is loaded quickly to meet time-to-availability requirements, then device becomes operational faster, but processor load increases
Solution Approach 1:
The device implements self-service configuration by incorporating a DMA-capable bus interface module that can autonomously transfer second stage configuration data from host system memory to the programmable logic without requiring continuous processor intervention. The storage interface circuit and internal configuration access interface enable this autonomous operation, significantly reducing processor load while maintaining fast configuration speeds.
Solution Approach 2:
A DMA engine is introduced as an intermediary between the host system memory and the programmable logic configuration memory. This intermediary handles the bulk data transfer operations, freeing the processor from direct involvement in the configuration data loading process while enabling high-speed transfers that meet time-to-availability requirements.
3Speed
If traditional memory interface is used for configuration data transfer, then interface is simple, but transfer speed is limited
Solution Approach 1:
The bus interface module is designed with multi-functionality, serving both as a standard bus interface for device communication and as a DMA-capable interface for high-speed configuration data transfer. This universal interface consolidates multiple functions into a single circuit, enabling high transfer speeds without proportionally increasing overall interface complexity.
Solution Approach 2:
The storage interface circuit and internal configuration access interface are merged with the bus interface module to create an integrated configuration system. This merging allows the same physical interface to handle both standard bus operations and high-speed DMA transfers, achieving fast transfer speeds while minimizing the increase in interface complexity through shared hardware resources.
Data Source
AI summary
Using a storage interface circuit of a programmable IC, a first set of configuration data can be communicated between a storage circuit and the programmable IC. Using the first set of configuration data, the programmable IC can be programmed to include: a bus interface module that is designed to interface with a host device over a communication bus that links multiple devices, and an internal configuration access interface that is designed to interface between the bus interface module and programmable logic of the programmable IC. Using direct memory access (DMA) transfers through the bus interface module, a second set of configuration data can be communicated between a memory circuit and the programmable IC. Using the second set of configuration data, the programmable logic of the programmable IC can be programmed.