DMA Queue Arbitration with Block Fragmentation to Prevent Starvation
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Solution Overview
Problem
Conventional direct memory access (DMA) techniques face inefficiencies due to the potential for one queue to be idle while processing large data blocks, leading to delayed processing of smaller data blocks in other queues, which diminishes data transfer efficiency.
Innovation Solution
A DMA engine with a DMA data arbiter and fragmenter is implemented to regulate and split large data blocks into smaller ones, ensuring timely processing of both larger and smaller data blocks by allowing the processing of smaller blocks between fragmented larger blocks, thus preventing queue starvation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA techniques process large data blocks from one queue, then data transfer capacity is improved, but other queues remain idle for exorbitant periods
Solution Approach 1:
The DMA system segments the processing of large data blocks by dividing them into smaller chunks. The arbiter interrupts processing of a large data block from one queue and switches to process smaller data blocks from other queues, ensuring that no single queue monopolizes the DMA engine for extended periods. This segmentation resolves the contradiction by maintaining high data transfer capacity while preventing excessive idle time in other queues.
Solution Approach 2:
The DMA arbiter dynamically adjusts queue processing priorities based on real-time conditions. When a queue with large data blocks is being processed, the arbiter can dynamically switch to other queues if they have pending smaller data blocks, creating a dynamic balance that prevents any single queue from remaining idle for exorbitant periods while maintaining overall high transfer capacity.
2Productivity
If the processor transfers data to and from memory, then data transfer is performed, but the processor cannot perform other functions
Solution Approach 1:
The patent extracts the data transfer function from the processor by implementing a dedicated DMA (Direct Memory Access) controller. The DMA controller handles all data transfer operations between memory and devices independently, allowing the processor to be taken out of the data transfer loop and focus exclusively on executing application programs and performing computational tasks, thereby resolving the contradiction between data transfer capability and processor versatility.
Solution Approach 2:
The DMA controller serves as an intermediary between the processor and memory/devices for data transfer operations. It receives transfer requests from devices, manages the actual data movement, and notifies the processor only when transfers are complete, allowing the processor to remain versatile while maintaining efficient data transfer capability through this intermediate controller.
Data Source
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AI summary
A direct memory access (DMA) engine may be responsible to enable and control DMA data flow within a computing system. The DMA engine moves blocks of data, associated with descriptors in a plurality of queues, from a source to a destination memory location or address, autonomously from control by a computer system's processor. Based on analysis of the data blocks linked to the descriptors in the queues, the DMA engine and its associated DMA fragmenter ensure that data blocks stored linked to descriptors in the queues do not remain idle for an exorbitant period of time. The DMA fragmenter may divide large data blocks into smaller data blocks to ensure that the processing of large data blocks does not preclude the timely processing of smaller data blocks associated with one or more descriptors in the queues. The data blocks stored may be two-dimensional data blocks.