DMA Register Bank Autonomous Transfer Control
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Solution Overview
Problem
Existing direct memory access methods in electronic systems are inefficient as they require significant CPU involvement and do not effectively manage data transfer cycles, leading to increased processing load and reduced system fluidity.
Innovation Solution
A method utilizing a direct memory access circuit with a register bank that allows for initialization, execution, and updating of data transfer cycles, including the use of signals to suspend or resume transfers, enabling dynamic adaptation of transfer cycles based on system state without constant CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct memory access methods are implemented with traditional CPU involvement, then data transfer can be initialized and concluded, but CPU load increases and system fluidity decreases
Solution Approach 1:
The DMA circuit autonomously manages data transfer operations by automatically initializing transfer cycles from memory, executing multiple transfer cycles without CPU intervention, and concluding transfers based on linked list items. The circuit updates register banks self-service style, reducing CPU load while maintaining transfer efficiency.
Solution Approach 2:
The system pre-loads a linked list of transfer cycle parameters into memory before DMA operations begin. This preliminary action allows the DMA circuit to execute multiple transfer cycles autonomously by sequentially accessing pre-prepared transfer parameters, eliminating the need for continuous CPU initialization.
2Productivity
If data transfer cycles are executed continuously, then productivity increases, but adaptability to system state changes decreases
Solution Approach 1:
The DMA circuit incorporates interrupt mechanisms that provide feedback to the CPU when specific conditions are met during data transfer operations. The circuit can pause transfer cycles, generate interrupt signals to notify the CPU of system state changes, and resume transfers after CPU intervention, enabling dynamic adaptation while maintaining overall productivity.
3Reliability
If CPU intervenes constantly to manage transfer cycles, then control precision increases, but loss of time increases
Solution Approach 1:
The data transfer operation is segmented into autonomous DMA-controlled phases and CPU-intervention phases. During autonomous phases, the DMA circuit handles multiple transfer cycles independently with high reliability. The CPU intervenes only at segment boundaries or when interrupts occur, minimizing time loss while maintaining control precision through structured segmentation of control responsibilities.
Data Source
AI summary
A register bank of a channel of a direct memory access circuit is initialized. Transfer cycles are executed as configured by the register bank, and updates are made to the registers from a memory. At each transfer cycle, an operation is performed in accordance with a first field of the register bank to either: carry on the execution or generate a first signal and suspend the execution. In response to each reception of the first signal by a central processing unit, an operation is performed to either: generate a second signal or modify the content of the register band and/or record into the memory a first item representative of a next update of the register bank. A second signal is then generated.