Non-Shadow Register Updates via DMA in Video Encoder

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Solution Overview

Problem

The challenge in video processing is updating non-shadow registers without causing distortion or flicker, particularly during the short vertical and horizontal blanking intervals, which are insufficient for software to program registers within the required time, especially when dealing with high-resolution video standards and increased processing demands.

Innovation Solution

Implementing a method to program non-shadow registers during the vertical blanking interval using a Direct Memory Access (DMA) engine, which allows for guaranteed updates without the need for shadow registers, enabling immediate changes to video parameters like PIP positioning, scaling, and brightness on a frame-by-frame basis without interrupting the display.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If software is used to program non-shadow registers during vertical blanking interval, then register updates can be performed, but the short duration of vertical blanking interval is insufficient for software programming

Engineering Contradiction:

Improveregister update timing precisionVSAvoidvertical blanking interval duration

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent replaces the software-based register programming mechanism with a hardware-based DMA engine. The DMA engine automatically transfers register update data from memory to the video processor during the vertical blanking interval, eliminating the time-consuming software programming sequence and achieving precise timing within the limited blanking window.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The system prepares register update data in advance in memory during the active video display period. The DMA engine is configured with the complete sequence of register updates before the vertical blanking interval begins, allowing immediate execution of all necessary register programming operations as soon as the blanking interval starts, without any software processing delay.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If shadow registers are used to update registers, then distortion and flicker can be avoided, but the patent aims to eliminate shadow register requirements

Engineering Contradiction:

Improvedisplay stabilityVSAvoidshadow register structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the shadow register component from the system by using the DMA engine to directly program non-shadow registers during the vertical blanking interval. This eliminates the need for the shadow register buffer structure while maintaining display stability through precise timing of register updates when no video is being displayed.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The DMA engine serves as an intermediary mechanism that enables direct programming of non-shadow registers during the vertical blanking interval. It acts as a bridge between memory and the video processor registers, transferring update data automatically without requiring shadow registers as an intermediate buffer, thus simplifying the overall system architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of operation

If CPU is used to control all nodes and respond to interrupt requests, then task scheduling can be performed, but processing capabilities and power consumption increase

Engineering Contradiction:

Improvetask scheduling capabilityVSAvoidCPU power consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

The DMA engine operates autonomously to handle register update data transfers during the vertical blanking interval without requiring CPU intervention. The system configures the DMA engine in advance, and it automatically executes the register programming sequence, freeing the CPU from this specific task and reducing overall CPU power consumption while maintaining full task scheduling capability.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The system uses the periodic vertical blanking interval as a trigger for automatic register updates. The DMA engine is configured to execute register programming at each vertical blanking interval without CPU intervention, creating a periodic autonomous operation pattern that reduces CPU workload and power consumption while ensuring timely register updates.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS8855194B2Updating non-shadow registers in video encoder

Publication Date: 2014.10.07 TEXAS INSTRUMENTS INC

AI summary

A video processor controlled by a set of non-shadow registers is provided. A list of updates for one or more of the non-shadow registers may be prepared in a memory module. A frame buffer is updated with video data for a display coupled to the video processor. A blanking interval is detected after updating the frame buffer. A direct memory access engine is triggered to transfer the list of updates from the memory module to the non-shadow registers during the blanking interval.