DMA Remapping Circuit Address Translation
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Solution Overview
Problem
Existing I/O management techniques in microprocessor architecture face limitations in functionality, performance, and robustness due to software-only I/O virtualization, which restricts guest operating systems and applications, and requires emulation or proxying of I/O operations, affecting overall platform robustness.
Innovation Solution
The implementation of a DMA remapping circuit that supports direct assignment of I/O devices to virtual machines, using multi-level page tables for address translation and capability indicators to enhance performance and robustness by translating guest physical addresses to host physical addresses, allowing direct interaction with physical device hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-only I/O virtualization is used to support VM I/O, then I/O virtualization functionality is provided, but performance deteriorates due to emulation and proxying of I/O operations
Solution Approach 1:
The patent replaces software-based I/O virtualization mechanisms with a hardware I/O memory management unit (I/O MMU) that performs address translation in hardware. This substitution eliminates the need for software emulation and proxying of I/O operations, directly resolving the performance degradation caused by software-only approaches while maintaining I/O virtualization functionality.
Solution Approach 2:
The patent introduces an I/O MMU as an intermediary hardware component between the guest I/O operations and the physical device hardware. This intermediary performs address translation and enables direct I/O operations without requiring software mediation, thus improving performance while maintaining the virtualization functionality.
2Adaptability or versatility
If software-only I/O virtualization is used, then I/O virtualization is achieved, but robustness deteriorates due to device drivers running in privileged VMM software
Solution Approach 1:
The patent segments the I/O virtualization functionality into distinct components: the hardware I/O MMU handles address translation and isolation, while the guest operating system maintains control of device drivers. This segmentation removes device drivers from the privileged VMM software context, improving platform robustness by isolating potential failure points while preserving I/O virtualization capability.
Solution Approach 2:
The I/O MMU acts as an intermediary that enforces memory protection and isolation between guest virtual address spaces and host physical address space. This hardware-mediated isolation improves robustness by preventing unauthorized access and isolating faults to individual guest contexts, while maintaining full I/O virtualization functionality.
3Productivity
If specialized translation structures are used, then address translation is provided, but adaptability deteriorates due to support for specific devices or limited usage models only
Solution Approach 1:
The patent implements a universal I/O MMU with a multi-level page table architecture that can handle various address translation scenarios (1:1 mapping, many-to-one mapping, I/O virtualization) through a single unified structure. This universal design maintains high translation performance while providing broad adaptability to support multiple device types and usage models, eliminating the limitation of specialized translation structures.
Solution Approach 2:
The patent employs dynamic multi-level page tables that can be configured and modified at runtime to accommodate different address translation requirements. The page table structure adapts to various usage scenarios through software configuration rather than requiring specialized hardware structures for each case, thus maintaining both performance and adaptability.
4Productivity
If general I/O memory management units are used, then address translation is provided, but adaptability deteriorates due to support for limited address space size or complexity
Solution Approach 1:
The patent implements a nested multi-level page table structure where higher-level page tables reference lower-level page tables, enabling support for large address spaces through hierarchical organization. This nested structure allows the I/O MMU to handle complex address translations for large address spaces while maintaining efficient hardware-based translation performance, overcoming the limitations of flat or single-level translation structures.
Data Source
AI summary
An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.