DMA Request Issuance Using Bus Latency and Buffer Residence Feedback
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Solution Overview
Problem
Existing direct memory access (DMA) devices do not efficiently manage bus latency and buffer residence time, leading to suboptimal performance in data transfer to accelerators.
Innovation Solution
A DMA device that calculates average bus latency and buffer residence time, adjusting its issuing capability based on these metrics to optimize data transfer to accelerators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the DMA device issues read requests at a fixed high rate, then the data transfer throughput is improved, but the bus latency increases and buffer residence time becomes suboptimal
Solution Approach 1:
The patent applies dynamics by making the read request issuing capability adjustable rather than fixed. The read request issuing circuit dynamically modifies its issuing capability based on feedback from the read buffer managing circuit about average bus latency and average buffer residence time, allowing the system to adapt to changing conditions and optimize performance
Solution Approach 2:
The patent implements feedback through the read buffer managing circuit that monitors actual bus latency and buffer residence time, then feeds this information back to the read request issuing circuit. This closed-loop control enables the DMA device to adjust its read request issuance rate based on real-time system conditions, resolving the contradiction between throughput and latency
2Productivity
If the DMA device increases issuing capability to improve performance, then data transfer speed is improved, but the buffer residence time becomes suboptimal when bus latency is high
Solution Approach 1:
The read buffer managing circuit provides feedback about average buffer residence time to the read request issuing circuit, which uses this information to adjust issuing capability. This feedback mechanism ensures that issuing capability is optimized based on actual buffer performance, preventing suboptimal residence times
Solution Approach 2:
The patent changes the parameter of issuing capability dynamically based on measured system conditions. The read request issuing circuit modifies this parameter in response to feedback about buffer residence time and bus latency, allowing the system to maintain optimal performance across varying operating conditions
Data Source
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AI summary
A direct memory access (DMA) device includes a controller, a read request issuing circuit issuing a read request based on issuing capability and storing an issuing time of the read request, a read buffer temporarily storing read data corresponding to the read request and storing an arrival time of the read data, and a read buffer managing circuit that counts a current time, calculates an average bus latency based on the issuing time of the read request when receiving the read data from the memory device, and calculates an average buffer residence time based on the arrival time of the read data when the read data stored in the read buffer is output to the accelerator. The read request issuing circuit adjusts the issuing capability based on the average bus latency and the average buffer residence time and issues the read request based on the adjusted issuing capability.