DMA Request Size Adaptation for Bus Arbitration Latency
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Solution Overview
Problem
Conventional DMA systems generate fixed-size requests, leading to inefficiencies and latency, especially in high-bandwidth networks, as they cannot transfer additional data available between request generation and arbitration, resulting in suboptimal data movement.
Innovation Solution
A method and system where a DMA module generates requests based on a minimum data transfer size and modifies the size dynamically based on available buffer slots before arbitration, allowing for adaptive data transfer sizing during bus access arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a DMA channel generates a request with a fixed or minimum frame size, then the DMA request complies with interface protocol requirements, but the DMA channel cannot transfer additional data available for transfer, resulting in latency
Solution Approach 1:
The patent applies dynamics by making the DMA request size adjustable and adaptive rather than fixed. The system dynamically modifies the data transfer size based on available buffer slots, allowing the DMA channel to transfer more data when available, thus improving productivity while reducing latency caused by fixed-size constraints
Solution Approach 2:
The patent changes the parameter of data transfer size from a fixed minimum value to a variable parameter that can be modified based on buffer availability. This allows the system to optimize transfer efficiency by adjusting the size parameter according to actual data availability and buffer capacity
2Productivity
If a DMA channel generates a request with a larger data transfer size, then more data can be transferred in a single request, but the request may exceed buffer slot capacity or interface protocol requirements
Solution Approach 1:
The patent implements feedback by continuously monitoring buffer slot status and using this information to adjust the DMA request size. The system receives feedback about available buffer capacity and protocol constraints, then modifies the transfer size accordingly to maximize data movement while ensuring protocol compliance and preventing buffer overflow
Solution Approach 2:
The system dynamically adjusts the request size parameter based on real-time buffer status and protocol requirements, allowing flexible optimization of transfer volume without compromising reliability or compliance
3Reliability
If a DMA channel breaks up a DMA data transfer request into smaller requests, then the requests comply with interface protocol requirements, but multiple arbitration cycles are needed, increasing latency
Solution Approach 1:
The patent merges multiple small DMA requests into a single larger request by accumulating available data in buffer slots and submitting them together. This reduces the number of arbitration cycles needed, thereby reducing latency while maintaining protocol compliance through controlled merging within protocol limits
4Productivity
If the DMA request size is increased to transfer multiple frames, then data transfer efficiency improves, but the complexity of managing buffer slots and arbitration increases
Solution Approach 1:
The patent applies self-service by implementing automatic buffer status monitoring and request size adjustment mechanisms. The DMA system autonomously manages buffer slots and adapts request sizes based on available capacity, reducing the need for complex external control logic while maintaining high transfer efficiency
Data Source
AI summary
Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system, wherein a size of data transfer is specified in the DMA request and is based on a minimum data transfer size; and submitting the DMA request to an arbitration module to gain access to a bus for transferring the information and while the arbitration module arbitrates between pending DMA requests, the DMA module monitors status from plural buffer slots and before the DMA request is granted, the DMA module modifies the size of data transfer based on available buffer slots.