DMA Reset Handling for Cryptographic Security
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Solution Overview
Problem
During cryptographic operations, untrusted system software can mask critical security faults, potentially exposing data by resetting DMA circuits before secure software can handle errors, leading to vulnerabilities in data protection.
Innovation Solution
A secure reporting path and reset-handling logic are implemented, where the DMA engine sets interrupt status bits and reports errors to a secure processor, holding any reset signal from untrusted software until the secure processor clears these bits, ensuring that security faults are handled before allowing a reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If untrusted system software is allowed to reset the DMA circuit freely, then the system response time is improved, but data security deteriorates because critical security faults can be masked
Solution Approach 1:
A secure processor acts as an intermediary between the untrusted system software and the DMA circuit. The secure processor receives reset requests from system software, verifies that critical security faults have been handled, and then authorizes the reset. This mediator ensures that data security is maintained while still allowing timely system response.
Solution Approach 2:
The system performs preliminary actions by requiring the secure processor to verify and handle critical security faults before allowing the reset to occur. The DMA circuit sets interrupt status bits when errors are detected, and the secure processor must clear these bits before the reset is permitted, ensuring security checks are completed in advance.
2Reliability
If the DMA circuit holds reset signals until secure processor clears interrupt status bits, then data security is improved, but system productivity deteriorates due to delayed reset
Solution Approach 1:
The system implements feedback through interrupt status bits that provide real-time information about security fault states. The DMA circuit sets these bits when errors occur, and the secure processor clears them when faults are handled. This feedback mechanism allows the system to make informed decisions about when to permit resets, balancing security requirements with system productivity.
Data Source
AI summary
Apparatuses, systems, and techniques for handling faults by a direct memory access (DMA) engine. When a DMA engine detects an error associated with an encryption or decryption operation, the DMA engine reports the error to a CPU, which may be executing an untrusted software directing a DMA operation, and the secure processor. The DMA engine waits for clearance from the secure processor before responding to further directions from the potentially untrusted software.