DMA Router Action Groups for Fewer Core Interruptions
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Solution Overview
Problem
Conventional system-on-chip (SoC) configurations face inefficiencies due to frequent processing core interruptions caused by multiple DMA channel triggers, leading to prolonged core disturbances and suboptimal task distribution between processing cores and DMA controllers.
Innovation Solution
A dedicated DMA router system that routes DMA triggers using a hardware block to manage DMA actions without interrupting processing cores, allowing for the creation of action groups that combine DMA operations and enforce dependencies, thereby offloading simpler tasks to DMA controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DMA channels are triggered to handle interrupts, then data transfer capability is improved, but processing core interruptions increase and core disturbance duration increases
Solution Approach 1:
A DMA router is introduced as an intermediary component between DMA controllers and processing cores. The router receives interrupt signals from multiple DMA channels and consolidates them into a single interrupt signal that triggers only one processing core, thereby maintaining data transfer capability while reducing core disturbance duration
Solution Approach 2:
The patent merges multiple DMA channel interrupts into a single consolidated interrupt signal. By combining the interrupt handling function into one core rather than distributing it across multiple cores, the system reduces the total number of context switches and core disturbances while maintaining the ability to handle multiple DMA transfers
2Adaptability or versatility
If processing cores handle complex data transfer tasks, then task flexibility is improved, but processing core productivity decreases due to frequent interruptions
Solution Approach 1:
The patent extracts simple data transfer tasks from processing cores and assigns them to DMA controllers. By removing these routine tasks from core responsibility, cores are freed to focus on complex computational work while DMA controllers handle the repetitive data movement operations
Solution Approach 2:
The system segments task handling by separating data transfer operations from computational operations. DMA controllers handle simple data transfer tasks independently, while processing cores focus on complex computations, creating a clear division of labor that improves overall system productivity
3Productivity
If simpler background tasks are handled by interrupting processing cores, then task completion is improved, but core disturbance frequency increases
Solution Approach 1:
The DMA router serves as an intermediary that handles background tasks and housekeeping operations independently of processing cores. By routing these simpler tasks through the router rather than directly to cores, the system maintains task completion while significantly reducing core disturbance frequency
Data Source
AI summary
A direct memory access (DMA) router including interrupt inputs, action groups and a DMA router engine. Each interrupt input is configured to receive a corresponding interrupt signal. Each action group is associated with a corresponding interrupt input and is configured with at least one DMA action, in which each DMA action is configured to select a DMA controller and a corresponding channel. The DMA router is configured to initiate a transfer using a selected channel of a selected DMA controller for at least one DMA action listed in an action group associated with a corresponding interrupt input triggered by assertion of a corresponding interrupt signal. The DMA actions may indicate dependencies, such that the DMA router may initiate a second DMA action only after completion of a first DMA action within the same action group based upon the indicated dependency.