DMA Router Action Group Scheduling for SoC Interrupt Offloading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional system-on-chip (SoC) configurations face inefficiencies due to frequent processing core interruptions from multiple DMA channels, leading to prolonged disturbances and inefficient task handling, with complex tasks often being handled by processing cores instead of DMA controllers to avoid excessive interruptions.
Innovation Solution
A dedicated DMA router is introduced to handle DMA requests, routing interrupts away from processing cores and using action groups to combine cross-SoC DMAs, allowing simultaneous or dependent DMA actions across multiple channels, thereby offloading tasks from processing cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple interrupts are triggered to handle multiple DMA channels, then all DMA channels can be serviced, but processing cores are disturbed longer and system performance deteriorates
Solution Approach 1:
The patent introduces an interrupt controller as an intermediary component between DMA channels and processing cores. The interrupt controller receives interrupts from multiple DMA channels and consolidates them into a single interrupt signal that is then forwarded to the processing core. This mediator approach allows complete servicing of all DMA channels while minimizing disruption to the processing core by reducing the number of context switches required.
Solution Approach 2:
The patent merges multiple interrupt signals from different DMA channels into a single consolidated interrupt. The interrupt controller combines multiple interrupt requests and generates one unified interrupt signal to the processing core. This merging strategy ensures that all DMA channels are acknowledged and serviced while reducing the total number of interruptions to the processing core, thereby maintaining system performance.
2Adaptability or versatility
If complex tasks are handled by processing cores instead of DMA controllers, then task handling flexibility is improved, but processing cores are overburdened and productivity decreases
Solution Approach 1:
The patent segments task handling responsibilities by separating simple background tasks from complex application tasks. The interrupt controller is configured to automatically handle simple tasks such as memory management, housekeeping operations, and data transfers through DMA channels. Complex tasks requiring decision-making and processing remain with the processing cores. This segmentation allows processing cores to focus on high-value complex tasks while maintaining high throughput, and simple tasks are handled autonomously by DMA controllers.
Solution Approach 2:
The patent enables DMA controllers to self-service by autonomously handling simple background tasks without requiring processing core intervention. The interrupt controller allows DMA controllers to independently manage memory operations, data transfers, and housekeeping functions. This self-service capability frees processing cores from routine tasks, improving overall system productivity while maintaining the flexibility needed for complex tasks.
3Speed
If frequent interrupts are used to handle background tasks, then task responsiveness is improved, but processing core interruptions increase and system efficiency worsens
Solution Approach 1:
The patent establishes continuous background task handling through DMA controllers that operate independently of processing core interrupt cycles. The interrupt controller enables DMA channels to continuously service background tasks such as memory management and data transfers without causing processing core interruptions. This continuous operation maintains system responsiveness for background tasks while preserving processing core productivity for application tasks.
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
A direct memory access (DMA) router including interrupt inputs, action groups and a DMA router engine. Each interrupt input is configured to receive a corresponding interrupt signal. Each action group is associated with a corresponding interrupt input and is configured with at least one DMA action, in which each DMA action is configured to select a DMA controller and a corresponding channel. The DMA router is configured to initiate a transfer using a selected channel of a selected DMA controller for at least one DMA action listed in an action group associated with a corresponding interrupt input triggered by assertion of a corresponding interrupt signal. The DMA actions may indicate dependencies, such that the DMA router may initiate a second DMA action only after completion of a first DMA action within the same action group based upon the indicated dependency.