DMA Safe Linked Lists for Double Buffering

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Solution Overview

Problem

Current safety systems for microcontrollers are inefficient in managing memory buffers, leading to potential missed samples or control signals, which can result in dangerous conditions due to processor overload and resource allocation issues.

Innovation Solution

Implementing a double-buffer system with Direct Memory Access (DMA) and safe linked lists, where a DMA controller manages data transfer between peripherals and memory buffers, using transaction control sets to alternate data between two buffers and verify proper execution, thereby reducing processor overhead and enhancing safety by preventing missed samples or control signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single memory buffer is used for data transfer, then the system structure is simple, but the processor may miss critical data or control signals due to overload

Engineering Contradiction:

Improvedata transfer reliabilityVSAvoidmemory buffer structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The single memory buffer is segmented into two separate buffers (first memory buffer and second memory buffer) that operate in parallel. The DMA controller alternates between these two buffers, transferring data to one while the other is being processed, thereby preventing data loss during processor overload without requiring complex arbitration mechanisms.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system prepares both memory buffers in advance before data transfer begins. The DMA controller is pre-configured with transaction control sets for both buffers, allowing it to immediately switch between buffers without requiring processor intervention when one buffer becomes full, thus preventing missed data signals.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If the processor manages memory buffer allocation, then resource allocation is flexible, but processor overhead increases leading to missed samples

Engineering Contradiction:

Improveprocessor efficiencyVSAvoidsample capture reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The memory buffer management function is extracted from the processor and assigned to the DMA controller. The DMA controller independently manages data transfer between peripherals and memory buffers using pre-loaded transaction control sets, freeing the processor from this overhead-intensive task while ensuring reliable sample capture through automated buffer switching.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The DMA controller performs self-service by autonomously managing the double-buffering mechanism. It automatically switches between the first and second memory buffers based on their fill status, verifies transaction completion, and handles error conditions without requiring processor intervention, thereby maintaining sample capture reliability while improving processor efficiency.

Inventive Principle:

Principle #25Self-service

3Reliability

If double buffering is implemented without DMA, then buffer management is possible, but processor overhead remains high and resource allocation is inefficient

Engineering Contradiction:

Improvedata transfer safetyVSAvoidprocessor energy consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The DMA controller serves as an intermediary between the processor and memory buffers. It handles all data transfer operations, buffer switching, and verification tasks, allowing the processor to focus on higher-level processing. This intermediary role eliminates the need for the processor to directly manage buffer allocation and data transfer, reducing energy consumption while maintaining data transfer safety.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Device complexity

If traditional single buffer is used, then resource allocation is simple, but dangerous conditions may occur due to missed control signals

Engineering Contradiction:

Improvebuffer management structureVSAvoidmissed control signals

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The system implements prior cushioning by maintaining two memory buffers ready for data transfer. When one buffer is being processed, the other is already prepared to receive incoming data, creating a safety cushion that prevents missed control signals even if the processor is overloaded or delayed in processing the current buffer.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10635615B2Safe double buffering using DMA safe linked lists

Publication Date: 2020.04.28 INFINEON TECHNOLOGIES AG

AI summary

A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.