DMA Scatter Gather for Non-Contiguous Memory Transfers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DMA technologies are inefficient when transferring non-contiguous memory blocks, requiring numerous descriptors and multiple system memory accesses, leading to increased latency and reduced data transfer efficiency.
Innovation Solution
A DMA controller and method that load DMA transfer descriptors to determine which memory elements within a contiguous block are included in the transfer, allowing for the identification of non-contiguous sub-blocks and performing transfers based on these determinations, reducing the need for multiple descriptor accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If DMA transfers break down large blocks into individual contiguous block transfers with separate descriptors, then the DMA controller can handle non-contiguous memory transfers, but the number of descriptor accesses to system memory increases significantly
Solution Approach 1:
The patent segments the descriptor access process by dividing the contiguous memory block into multiple sub-blocks that can be transferred in parallel. Each sub-block has its own descriptor, but these descriptors are accessed and processed simultaneously rather than sequentially, reducing the total time spent on descriptor accesses while maintaining the ability to handle non-contiguous transfers.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by enabling multiple DMA channels to operate simultaneously on different sub-blocks of the same descriptor. This transforms the traditional single-channel sequential descriptor access into a multi-channel parallel operation, significantly reducing latency while preserving adaptability for non-contiguous memory transfers.
2Adaptability or versatility
If multiple descriptors are used to define different portions of memory to be transferred, then non-contiguous memory blocks can be transferred, but the device complexity and number of data structures increase
Solution Approach 1:
The patent creates a universal descriptor structure that can handle both contiguous and non-contiguous memory transfers through a single data structure. The descriptor includes fields for source address, destination address, transfer count, and a flag indicating whether the transfer is contiguous or non-contiguous. This multi-functional descriptor eliminates the need for separate descriptor types or additional data structures, reducing device complexity while maintaining full adaptability.
3Productivity
If the CPU offloads memory transfer operations to DMA controller, then the CPU can perform other work during transfer, but the CPU is still occupied during descriptor setup and access
Solution Approach 1:
The patent implements preliminary action by having the CPU set up all descriptor information in advance and store it in DMA controller's internal memory before initiating the transfer. The DMA controller then autonomously manages all descriptor accesses without further CPU intervention. This preliminary setup phase allows the CPU to completely offload descriptor management to the DMA controller, maximizing CPU availability for other operations while minimizing the time the CPU is occupied with descriptor-related tasks.
Data Source
AI summary
A direct memory access (DMA) controller, includes circuitry configured to load a DMA transfer descriptor configured to define which memory elements within a contiguous block of n memory elements are to be included in a given DMA transfer. The circuitry is further configured to, based on the DMA transfer descriptor, determine whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, including a determination that two or more non-contiguous sub-blocks of memory elements within the contiguous block of n memory elements are to be transferred. The circuitry is further configured to, based on the determination of whether each memory element within the contiguous block of n memory elements is to be included in the given DMA transfer, perform the DMA transfer of memory elements determined to be included within the given DMA transfer.