DMA Scheduling for Fragmented Buffer Packet Transmission
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DMA systems face inefficiencies when handling network packets with arbitrary alignments and sizes, leading to costly data manipulation and fragmentation issues during transmission.
Innovation Solution
A DMA scheduling mechanism and system that interleave data transfers on multiple I/O ports using a polled interface, allowing efficient handling of packet fragments with different octet alignments and enabling insertion of additional data fields, by using a processor to manage DMA operations and handle packet concatenation and alignment through a combination of hardware and software components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA reads whole words from memory, then data transfer rate is improved, but packet alignment compatibility deteriorates
Solution Approach 1:
The packet data is segmented into multiple fragments stored in separate memory buffers with different alignments. The DMA system processes each fragment independently through separate DMA transfers, allowing each transfer to be optimally aligned while maintaining overall packet integrity through software reassembly.
Solution Approach 2:
A software intermediary layer is introduced between the DMA subsystem and the packet processing logic. This software layer manages the fragmentation, coordinates multiple DMA transfers, and reassembles the packet data, allowing the DMA hardware to operate at full speed while handling misaligned data through software coordination.
2Productivity
If packet data is kept contiguous in memory, then DMA transfer efficiency is improved, but protocol conversion cost increases
Solution Approach 1:
Instead of maintaining contiguous packet data, the system segments the packet into multiple fragments that can be stored in separate memory buffers. This eliminates the need for costly memory copying and contiguity maintenance while allowing DMA to transfer each fragment efficiently from its own buffer.
Solution Approach 2:
Each packet fragment independently manages its own memory buffer and alignment characteristics. The DMA system services each fragment autonomously through separate transfers, eliminating the need for centralized memory management and costly data manipulation operations.
3Adaptability or versatility
If protocol conversion inserts octets into packet, then network standard adaptability is improved, but memory manipulation cost increases
Solution Approach 1:
The software intermediary layer handles protocol conversion by inserting required octets into the packet data structure in memory. This software-based approach allows flexible protocol adaptation without requiring complex hardware memory manipulation circuits, reducing overall system complexity while maintaining adaptability.
Data Source
AI summary
The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.