DMA-Based Scheduler Skew Tuning for Real-Time Synchronization
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Solution Overview
Problem
Existing control systems face challenges in achieving precise real-time synchronization between processing systems, particularly in avoiding single event upsets and busy waiting issues associated with shared real-time clocks and handshake messages.
Innovation Solution
A system that utilizes a direct memory access controller to trigger interrupts for synchronization messages between processing systems, determining time differences to adjust the synchronization skew of a real-time scheduler, allowing for autonomous message transfer and task execution without processor intervention, thereby maintaining synchronization and optimizing execution frame times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a shared real-time clock is used for synchronization, then close synchronization is achieved, but the system risks single event upsets affecting multiple systems and requires dedicated signal paths
Solution Approach 1:
The patent divides the synchronization function into separate segments: each processing system maintains its own independent real-time clock rather than sharing a single clock. This segmentation isolates potential failures to individual systems while maintaining synchronization through coordinated message exchange and skew adjustment, resolving the contradiction between precision and reliability.
Solution Approach 2:
The patent introduces synchronization messages as an intermediary mechanism between processing systems. These messages carry timestamp information that enables systems to calculate and adjust their relative skew without direct clock sharing, achieving precise synchronization while maintaining system independence and reliability.
2Measurement precision
If handshake and acknowledgement messages are exchanged between processing systems, then synchronization is achieved, but busy waiting occurs as systems continually poll receiver registers
Solution Approach 1:
The patent implements self-service synchronization where each processing system autonomously sends synchronization messages with timestamps and automatically calculates the skew based on received timestamps. This eliminates the need for continuous polling and busy waiting, as systems independently manage their own synchronization without requiring constant active monitoring of receiver registers.
Solution Approach 2:
The patent employs periodic synchronization message exchange instead of continuous polling. Systems send synchronization messages at defined intervals and adjust skew based on accumulated timing information, eliminating busy waiting while maintaining synchronization precision through periodic rather than continuous operation.
3Measurement precision
If processor cores actively manage synchronization message transfer, then synchronization control is maintained, but processor resources are consumed and other tasks are delayed
Solution Approach 1:
The patent implements self-service message transfer through the direct memory access controller, which autonomously handles sending and receiving synchronization messages without processor core intervention. The processor cores only perform high-level configuration and skew adjustment, while the DMA controller manages the actual data transfer, freeing processor resources for other tasks and improving overall productivity.
Solution Approach 2:
The patent introduces the direct memory access controller as an intermediary between the processor cores and the communication interface. This intermediary handles the time-consuming message transfer operations, allowing processor cores to focus on critical synchronization logic and other computational tasks, thereby resolving the contradiction between synchronization precision and processor productivity.
Data Source
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AI summary
A system (200) includes a memory system (205A, 205B) and a processor (204A) of a first processing system (202A) including a processor core (210A), a direct memory access controller (214A), and a communication interface (222A). The processor core (210A) is configured to execute a plurality of instructions to configure the direct memory access controller (214A) to trigger a transmitter interrupt upon transmitting a first synchronization message through the communication interface (22A) to a second processing system (202B), configure the direct memory access controller (214A) to trigger a receiver interrupt upon receiving a second synchronization message from the second processing system (202B), determine a time difference between triggering of the transmitter interrupt and the receiver interrupt, and adjust a synchronization skew of a real-time scheduler based on the time difference to tune real-time synchronization between the first processing system (202A) and the second processing system (202B).