DMA Storage Controller Bypasses CPU for Low Latency Access
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Solution Overview
Problem
Distributed storage systems face high and unpredictable latency due to mismatched usage patterns between processor and storage resources, leading to inefficiencies and additional overheads in servicing storage access requests.
Innovation Solution
Implementing direct memory access (DMA) engines for storage and network controllers to eliminate CPU loads and data copying, allowing client-server processes to manage buffer memory and register direct memory accessible regions, thereby reducing processor involvement in data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processor resources are used to service storage access requests, then storage requests can be processed, but latency becomes high and unpredictable due to heavy processor utilization
Solution Approach 1:
The patent extracts the data transfer function from the processor by implementing direct memory access (DMA) between storage devices and memory. The processor no longer needs to service every data transfer request, as the DMA controller handles data movement independently, thereby reducing processor utilization and improving storage access latency
Solution Approach 2:
The system enables self-service by allowing storage devices to directly access and transfer data to memory without requiring processor intervention for each transfer operation. The DMA controller autonomously manages data movement, freeing the processor to handle higher-level computing tasks while storage operations proceed independently
2Ease of operation
If data is transferred through kernel space and user space, then proper memory management is achieved, but additional copying overhead increases processor cost
Solution Approach 1:
The patent removes the unnecessary kernel space to user space data copying step by implementing a direct path where storage devices transfer data directly to the application's buffer in user space through DMA. This eliminates the intermediate copying operation while maintaining proper memory management through direct buffer registration
Solution Approach 2:
The patent implements a universal buffer management approach where applications can register their buffer memory regions for direct access by both storage controllers and network interface controllers. This multi-functional buffer pool serves both storage I/O and network I/O operations, eliminating the need for separate kernel-mediated transfer paths
Data Source
AI summary
A method of processing client requests that includes receiving a client request from a client for access to data, issuing a direct memory access command to non-transitory storage resources to load data to a target memory location without accessing the target memory location, and instructing a network interface controller in communication with the storage resources to send a response to the client. The response includes an information portion and a data portion.