DMA Transfer Parameter Sharing for Multiprocessor Load Reduction

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Solution Overview

Problem

Existing methods for sharing data between processors in multiprocessor systems either require costly shared memory or increase the load on the central processing unit (CPU) due to constant data transfer needs.

Innovation Solution

An information processing system that uses direct memory access (DMA) control units and communication units to generate and manage transfer parameters, allowing for efficient data transfer between processors without the need for shared memory, thereby reducing CPU load.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a shared memory is used to share data between processors, then data sharing capability is improved, but hardware cost increases

Engineering Contradiction:
Improvedata sharing capabilityVSAvoidhardware cost
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Instead of using a physical shared memory, the patent creates a virtual copy of the memory address space. Each processor has its own local memory, but through the DMA controller and communication unit, data is copied and transferred between processors' memory spaces, simulating shared memory access without requiring actual shared physical memory hardware.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces a communication unit and DMA controller as intermediary components between processors. These intermediaries handle the data transfer and address mapping, allowing processors to access each other's memory spaces without direct physical connection to a shared memory, thus reducing hardware complexity while maintaining data sharing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If data is transferred between processors to maintain same data in shared address space, then data consistency is improved, but CPU load increases

Engineering Contradiction:
Improvedata consistencyVSAvoidCPU load
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent extracts the data transfer control function from the CPU and assigns it to a dedicated DMA (Direct Memory Access) controller. The CPU only needs to generate the initial transfer parameter and trigger the transfer, while the DMA controller autonomously handles the actual data copying between memory spaces, significantly reducing CPU load while maintaining data consistency.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The DMA controller is designed to autonomously manage data transfer operations without continuous CPU intervention. Once the CPU provides the transfer parameter, the DMA controller self-manages the entire data copying process, including reading from one processor's memory, transmitting through the communication unit, and writing to the other processor's memory, thereby reducing CPU energy consumption.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11983127B2Information processing system, information processing method, and information processing device to reduce load on an information processing unit
Publication Date: 2024.05.14 SONY GROUP CORP
  • US11983127B2 patent drawing
  • US11983127B2 patent drawing
  • US11983127B2 patent drawing

AI summary

The present technology relates to an information processing system, information processing method, and information processing device capable of reducing load on an information processing unit in a case where data is shared among a plurality of information processing devices. There are included a first information processing device that controls DMA on the basis of a transfer parameter used for controlling transfer of data, and a second information processing device that communicates with the first information processing device, and controls DMA on the basis of the transfer parameter, in which the first information processing device generates the transfer parameter used for controlling reception of transfer data, and transmits the transfer parameter to the second information processing device, and the second information processing device controls reception of the transfer data from the first information processing device on the basis of the transfer parameter received from the first information processing device. The present technology can be applied to, for example, an apparatus including a multiprocessor system.