DMA Address Translation Tables for Reusable Memory Descriptors

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Solution Overview

Problem

The generation of memory descriptors on the fly during runtime for DMA transfers incurs significant latency, especially in scenarios where data locations are determined dynamically, impacting the execution of applications like object recognition.

Innovation Solution

A DMA engine is equipped with a local address translation table to store address translation information, allowing memory descriptors to be generated once and reused by translating logical addresses to actual addresses at runtime, reducing the need for repeated descriptor generation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory descriptors are generated on the fly during runtime for each DMA transfer, then the data transfer can accommodate dynamic data locations, but the DMA overhead and execution latency increase significantly

Engineering Contradiction:

Improvedynamic data location accommodationVSAvoidexecution latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent pre-generates memory descriptors with placeholder addresses during compilation or initialization, storing them in a descriptor cache. At runtime, the address translation mechanism replaces placeholder addresses with actual data locations using address translation tables, avoiding the need to generate descriptors from scratch for each transfer. This preliminary preparation significantly reduces runtime overhead while maintaining adaptability to dynamic data locations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces address translation tables as an intermediary layer between the pre-generated descriptors and actual data locations. The translation mechanism maps placeholder addresses to real data locations without requiring descriptor regeneration, thus reducing DMA overhead while accommodating dynamic data placements caused by memory allocation variability.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If memory descriptors are generated on the fly during runtime, then the latest data locations can be used, but host processing time for descriptor copying increases

Engineering Contradiction:

Improvedata location accuracyVSAvoidhost processing throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent creates a copy of the descriptor cache in the DMA engine's local memory, allowing the host to update address translation tables without repeatedly copying entire descriptor sets. The DMA engine independently accesses the copied descriptors and performs address translation using its local translation tables, significantly reducing host processing time while ensuring accurate data location information is used.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The address translation table acts as an intermediary that separates descriptor generation from data transfer execution. The host only needs to update translation tables with current data locations, while the DMA engine handles descriptor processing and address resolution independently, thereby maintaining data location accuracy without burdening the host with repeated descriptor copying operations.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Loss of time

If address translation tables are implemented in the DMA engine, then descriptor reuse is enabled, but the device complexity increases

Engineering Contradiction:

ImproveDMA overheadVSAvoidDMA engine structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent integrates address translation table functionality into the existing DMA engine architecture, allowing the same hardware structure to serve both traditional DMA transfer functions and the new address translation feature. The translation tables are implemented as extensions of the DMA engine's existing memory management capabilities, enabling descriptor reuse and reduced overhead without requiring completely separate translation hardware.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The address translation tables are nested within the DMA engine's existing address management structure. The translation tables store mappings that are seamlessly integrated into the DMA descriptor processing pipeline, allowing the DMA engine to perform address translation as part of its normal operation without adding significant external complexity. The nested structure enables compact implementation within the existing device footprint.

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS12524360B1Overhead reduction using address translation in direct memory accesses

Publication Date: 2026.01.13 AMAZON TECH INC

AI summary

Techniques to reduce direct memory access (DMA) overhead may include retrieving an address translation descriptor from a descriptor queue of a DMA engine, and updating an address translation table in the DMA engine with address translation information obtained from the location indicated by the address translation descriptor. A set of memory descriptors is then obtained from the descriptor queue. The set of memory descriptors can be processed by determining that the addresses in the set of memory descriptors are to be translated using the address translation table, and performing memory access operations by using the address translation table to translate the addresses in the set of memory descriptors.