DMA Unit Parallel Data Transfer in Storage Devices

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Solution Overview

Problem

Current data storage devices using nonvolatile memory devices face limitations in data processing speed due to the lack of efficient data transmission mechanisms between the nonvolatile memory device and the host device.

Innovation Solution

Incorporating a direct memory access (DMA) unit within the data storage device to manage data transmission between the nonvolatile memory device and the host device through a buffer memory, allowing parallel transmission of data, thereby enhancing data processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission is performed sequentially from nonvolatile memory device to buffer memory and then to host device, then device complexity is reduced, but data processing speed deteriorates

Engineering Contradiction:
Improvedata processing speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The data transmission path is segmented into two parallel channels: one for transferring data from nonvolatile memory device to buffer memory, and another for transferring data from buffer memory to host device. This segmentation allows simultaneous operation of both transmission paths, resolving the contradiction between improved data processing speed and device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Data is preliminarily transferred to the buffer memory from the nonvolatile memory device before being transferred to the host device. This preliminary action enables the buffer memory to serve as an intermediate staging area, allowing parallel transmission operations and improving overall data processing speed without significantly increasing device complexity.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If parallel data transmission is implemented through DMA unit, then data processing speed is improved, but device complexity increases

Engineering Contradiction:
Improvedata processing speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer memory serves as an intermediary component between the nonvolatile memory device and the host device, enabling parallel data transmission. The DMA unit utilizes this intermediary to perform simultaneous data transfers, improving data processing speed while keeping the increase in device complexity manageable through the use of a standard buffer memory component.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9785584B2Data storage device and method thereof
Publication Date: 2017.10.10 SK HYNIX INC
  • US9785584B2 patent drawing
  • US9785584B2 patent drawing
  • US9785584B2 patent drawing

AI summary

A data storage device includes a nonvolatile memory device; a buffer memory for storing temporarily data to be transmitted from the nonvolatile memory device to a host device or data to be transmitted from the host device to the nonvolatile memory device; a memory control unit for performing a control operation for controlling the nonvolatile memory device; and a direct memory access (DMA) unit for performing a data transmission operation associated with the buffer memory, according to control of the memory control unit, wherein the DMA block transmits a first data from the nonvolatile memory device to the buffer memory, and wherein the DMA unit transmits a second data from the nonvolatile memory device to the buffer memory, while the first data stored in the buffer memory is transmitted from the buffer memory to the host device.