DMA Vector Buffer for Non-Unity Strided Memory Access
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Solution Overview
Problem
The divergence in speed between increasingly complex processors and slower memory technologies limits the number of useful operations per second, leading to processor idle time and inefficient data access, particularly in parallel processing environments where data placement and synchronization issues are prevalent.
Innovation Solution
A processor architecture with an explicitly programmable, asynchronous DMA-based data pre-fetcher that synchronizes DMA transfers with the processing core, enabling efficient mapping of non-unity strided memory to local L1 memory and minimizing worst-case latency through guard bits and synchronized data pre-load/post-store operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If processor complexity and speed are increased, then processing capability is improved, but memory access efficiency deteriorates due to speed divergence
Solution Approach 1:
The patent implements a data pre-fetcher that proactively loads data from memory into local L1 memory before the processor needs it. This preliminary action eliminates processor idle time by ensuring data is already available when needed, resolving the speed divergence between fast processors and slow memory access
Solution Approach 2:
The patent introduces an asynchronous DMA-based pre-fetcher as an intermediary component between main memory and the processor. This mediator handles data transfer operations independently, allowing the processor to continue execution without waiting for memory access, thus improving overall system performance
2Productivity
If parallel processing is implemented, then processing throughput is improved, but data placement and synchronization issues worsen
Solution Approach 1:
The patent segments memory access operations by implementing separate pre-fetch channels and guard bit mechanisms for different data regions. This segmentation allows independent management of data placement for multiple parallel processing streams, reducing synchronization conflicts and simplifying data management complexity
3Reliability
If guard bits are used for synchronization, then data availability is ensured, but memory overhead increases
Solution Approach 1:
The patent applies guard bits selectively to specific data regions that require synchronization rather than uniformly across entire memory spaces. This localized application ensures data availability only where needed, minimizing unnecessary memory overhead while maintaining reliability for critical operations
Data Source
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AI summary
According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.