DMA Worker Threads for Heterogeneous Computing Resource Scheduling
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Solution Overview
Problem
Heterogeneous computing systems face inefficiencies in scheduling hardware resources for offloading functions to processing devices, leading to suboptimal data transfer and overall performance.
Innovation Solution
A runtime system is implemented that maintains write and read task queues and utilizes DMA worker threads to efficiently manage data transfer between a host processor and processing devices, adapting to the concurrent data transfer capabilities of the devices for concurrent and efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the host processor manages data transfer to and from processing devices, then data transfer can be performed, but the overall efficiency and performance of the heterogeneous computing system is suboptimal
Solution Approach 1:
The patent extracts the data transfer management function from the host processor and assigns it to dedicated DMA worker threads. These threads specifically handle data movement between host memory and processing device memory, separating this task from the host processor's computational workload and from general-purpose I/O handling, thereby optimizing system throughput and reducing data transfer time.
Solution Approach 2:
The patent introduces DMA (Direct Memory Access) worker threads as intermediary entities that mediate data transfer between the host processor and processing devices. These threads act as specialized intermediaries that manage the complexity of data movement, handle buffering, and coordinate transfers without burdening the host processor, thus improving overall system efficiency.
2Productivity
If multiple DMA worker threads are used to handle concurrent data transfer, then data transfer efficiency is improved, but system complexity increases
Solution Approach 1:
The patent segments the data transfer workload into multiple independent DMA worker threads, each capable of handling transfers concurrently. This segmentation allows parallel processing of data transfer tasks, improving throughput while keeping each individual thread relatively simple in structure, thus managing complexity through division rather than consolidation.
Solution Approach 2:
Each DMA worker thread is designed to be self-sufficient, independently managing its own data transfer tasks from the task queue without requiring complex coordination with other threads. This self-service approach reduces the need for sophisticated inter-thread communication and synchronization mechanisms, thereby limiting the growth of system complexity despite having multiple threads.
Data Source
AI summary
A heterogeneous computing system can include a host memory and a host processor. The host memory is configured to maintain a write task queue and a read task queue. The host processor is coupled to the host memory and a processing device. The host processor is adapted to store write tasks in the write task queue. The write tasks cause transfer of input data to the processing device. The processing device is adapted to perform offloaded functions. The host processor is adapted to store read tasks in the read task queue. The read tasks cause transfer of results from the offloaded functions from the processing device. The host processor is further adapted to maintain a number of direct memory access (DMA) worker threads corresponding to concurrent data transfer capability of the processing device. Each DMA worker thread is preconfigured to execute tasks from the write task queue or the read task queue.