Direct Memory Access Controller Non-Linear Data Transfer
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Solution Overview
Problem
Direct memory access controllers (DMAC) face challenges in managing disparate data transfers without interrupting the processor, particularly in scenarios requiring complex non-linear data sequences, which often result in increased gate count and power consumption due to the need for extensive storage of control information.
Innovation Solution
A DMAC design that stores two sets of control data for each channel in memory, allowing the controller to switch between them automatically, reducing the amount of data stored within the controller and enabling complex non-linear data transfers without processor intervention, thereby minimizing power consumption and gate count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If control information for each channel is stored in the DMA controller itself, then data transfer control is simplified and fast, but the gate count and storage requirements increase significantly
Solution Approach 1:
The patent extracts the control information storage function from the DMA controller and relocates it to external memory. The DMA controller retains only the essential control logic and pointers, while the detailed control information for each channel (source addresses, destination addresses, transfer sizes, transfer widths) is stored in external memory. This extraction reduces the gate count of the DMA controller while maintaining its ability to control data transfers efficiently.
Solution Approach 2:
The patent transitions from storing all control information within the DMA controller (one-dimensional storage) to a two-dimensional storage architecture where control information is distributed across external memory locations indexed by channel number. This dimensional change allows the system to scale without proportionally increasing the DMA controller's gate count, as control information for multiple channels is stored externally and accessed via pointers.
2Device complexity
If control information is stored in external memory with pointers in the DMA controller, then gate count is reduced, but processor intervention is required to update control data for disparate transfers
Solution Approach 1:
The patent implements preliminary action by pre-configuring control information blocks in external memory for each channel, including source addresses, destination addresses, transfer sizes, and transfer widths. The DMA controller is pre-loaded with pointers to these control blocks. When a data transfer is initiated, the DMA controller can immediately access the pre-prepared control information without requiring processor intervention during the actual transfer operation. This preliminary preparation enables the DMA controller to autonomously handle disparate data transfers.
Solution Approach 2:
The patent enables self-service by allowing the DMA controller to autonomously manage data transfers using control information stored in external memory. The controller reads control blocks from memory, executes the transfers independently, and updates its own pointers without requiring processor intervention. This self-service capability frees the processor to perform other tasks while the DMA controller handles data transfers autonomously, improving overall system productivity.
3Adaptability or versatility
If linked lists are used to manage disparate data transfers, then transfer flexibility is improved, but a register for each channel is required to store linked list pointers
Solution Approach 1:
The patent merges the control information storage and the linked list structure into a unified external memory architecture. Instead of maintaining separate registers in the DMA controller for each channel's linked list pointer, the system combines all control information (including what would traditionally be in linked lists) into external memory blocks. Each channel's control information is stored as a structured block in external memory, eliminating the need for dedicated registers in the DMA controller and reducing device complexity while maintaining transfer flexibility.
Data Source
AI summary
A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.