Self-Aligned DMOS Body Pickup via Blocking Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DMOS device manufacturing processes are limited by the capabilities of photo/masking equipment, which restricts the minimization of the N+/P+/N+ source/body region and increases fabrication costs due to the need for multiple masking steps.
Innovation Solution
The process employs spacers and gate blocking methods to define the N+/P+/N+ source/body region, reducing the reliance on photo/masking steps and enabling the formation of smaller source regions without requiring advanced photo/masking equipment, by using polysilicon and silicon nitride layers to form blocking spacers and ONO spacers that define the region boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo/masking steps are used to define N+/P+/N+ source/body region, then manufacturing precision can be achieved, but device complexity and manufacturing cost increase due to multiple masking steps
Solution Approach 1:
The polysilicon layer and blocking spacers automatically define the N+/P+/N+ source/body region boundaries through self-aligned formation. The gate structure itself serves as the alignment reference for subsequent doping steps, eliminating the need for external photo/masking equipment to define these regions. This self-service mechanism achieves precise region definition while reducing process complexity.
Solution Approach 2:
Blocking spacers are introduced as intermediary structures that wrap around the polysilicon layer and gate structures. These spacers act as temporary masks during ion implantation processes, defining the body pickup region and source regions without requiring photo/masking steps. The spacers are subsequently removed after serving their defining function.
2Manufacturing precision
If photo/masking equipment capability is used to define source/body region, then manufacturing precision is maintained, but ease of manufacture deteriorates due to requirement of advanced equipment
Solution Approach 1:
The patent replaces the mechanical/photo-masking system with a self-aligned structural formation approach. Instead of using photoresist patterns and masking layers that require advanced lithography equipment, the method uses deposited polysilicon layers and blocking spacers that are formed by standard thin-film deposition and etching processes. This substitution eliminates the need for high-end photo/masking equipment while achieving comparable or better precision through self-alignment.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning (photo/masking) to three-dimensional self-aligned structure formation. By stacking polysilicon layers, blocking spacers, and gate structures in multiple dimensions, the method defines region boundaries through vertical layering rather than horizontal patterning. This dimensional transition enables precise region definition using simpler, more widely available deposition and etching equipment.
3Manufacturing precision
If multiple masking steps are used for DMOS fabrication, then manufacturing precision is achieved, but productivity decreases due to increased process time
Solution Approach 1:
The patent merges multiple masking steps into a unified self-aligned process flow. The polysilicon layer formation, blocking spacer deposition, and gate structure creation are combined into a sequential self-aligned sequence where each step automatically aligns with the previous step. This merging eliminates the need for separate photo/masking operations for defining the N+/P+/N+ region, body pickup region, and source regions, significantly reducing the total number of process steps and cycle time.
Solution Approach 2:
The polysilicon layer and blocking spacers are formed in advance as self-aligned structures that pre-defin e the boundaries for subsequent doping steps. By performing these structural formations beforehand, the patent eliminates the need for time-consuming photo/masking operations during the actual doping process. The preliminary structures serve as built-in alignment references that guide subsequent ion implantation without requiring additional masking steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of source region size and significantly lowers the manufacturing cost of DMOS devices by minimizing the number of masking steps and overcoming equipment capability limitations, resulting in more efficient and cost-effective production.
Implementation Method 1
etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region
Implementation Method 2
implanting dopants of a second doping type through the window to the drift region to form a body region
Implementation Method 3
forming blocking spacers to wrap side walls of the polysilicon layer in a window of the polysilicon layer which is formed after etching
Implementation Method 4
implanting dopants of the second doping type into the body region under a window shaped by the blocking spacers to form a body pickup region
Implementation Method 5
forming ONO spacers to wrap side walls of the gates
Data Source
AI summary
A manufacturing process of a DMOS device in a drift region in a semiconductor substrate, having: forming a polysilicon layer above the drift region; forming a block layer above the polysilicon layer; etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region; implanting dopants through the window to the drift region to form a body region; forming blocking spacers to wrap side walls of the polysilicon layer; implanting dopants into the body region under a window shaped by the blocking spacers to form a body pickup region; etching away the blocking spacers; performing a masking step to form gates; forming ONO spacers to wrap side walls of the gates; and performing a masking step to form source regions and drain pickup regions.