DMOS Transistor Cavity SOI Breakdown Voltage
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Solution Overview
Problem
Conventional methods for increasing the breakdown voltage of lateral DMOS transistors, such as backside trench etching, complicate the process flow and require significant capital investment, while existing solutions do not effectively enhance the breakdown voltage while maintaining low on-state drain-to-source resistance.
Innovation Solution
A method of fabricating a DMOS transistor with a cavity in the bulk region of an SOI structure directly below the drift region, which reduces the lateral electric field through the RESURF principle, allowing for increased breakdown voltage and low on-state drain-to-source resistance by selectively etching openings and forming a cavity beneath the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside trench etching is used to increase breakdown voltage, then breakdown voltage is improved, but process complexity and capital investment increase significantly
Solution Approach 1:
Instead of etching from the backside of the substrate, the patent forms the cavity by etching from the front surface through openings in the insulator layer. This inverts the conventional approach, allowing cavity formation without complex backside processing while achieving the same electrical effect of reducing lateral electric field and increasing breakdown voltage
Solution Approach 2:
The cavity formation is segmented into multiple steps: forming openings through the insulator layer, etching the cavity in the bulk region, and selectively removing insulator material. This segmentation allows precise control of the cavity geometry and position beneath the drift region, achieving breakdown voltage enhancement without requiring entire substrate processing
2Ease of manufacture
If conventional lateral DMOS structure is used, then manufacturing is easier and cost is lower, but breakdown voltage is limited and on-state resistance is higher
Solution Approach 1:
The patent introduces a vertical dimension by forming a cavity beneath the drift region, transforming the conventional two-dimensional lateral structure into a three-dimensional structure. This dimensional change allows the lateral DMOS to achieve vertical DMOS-like breakdown voltage characteristics while maintaining lateral fabrication simplicity
Solution Approach 2:
The cavity geometry parameters (depth, width, position) are optimized to achieve the desired electrical characteristics. By controlling the cavity dimensions and its position beneath the drift region, the patent achieves breakdown voltage in excess of 700V while maintaining low on-state drain-to-source resistance, resolving the trade-off between manufacturing ease and electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves a breakdown voltage in excess of 700V with a low on-state drain-to-source resistance, enabling the transistor to handle higher drain voltage levels with improved performance and reduced manufacturing complexity.
Implementation Method 1
A method of fabricating a DMOS transistor with a cavity in the bulk region of an SOI structure directly below the drift region, which reduces the lateral electric field through the RESURF principle
Data Source
Figure 1~2
Figure 3~4
Figure 5A~5C
AI summary
A lateral DMOS transistor (300) formed on a silicon-on-insulator (SOI) structure (102) has a higher breakdown voltage that results from a cavity (310) that is formed in the bulk region (104) of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer (106) of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.