DMOS CMOS Integration via Segmented Ion Implantation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of DMOS and CMOS transistors into a single IC chip is complex and costly due to the need for a sophisticated manufacturing process, which complicates the semiconductor fabrication process and increases costs.
Innovation Solution
A method of fabricating semiconductor devices that includes forming separation regions using shallow trench isolation or deep trench isolation, followed by a series of ion implantation processes to create well regions and high concentration source and drain regions, reducing the number of mask patterns required compared to conventional methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a sophisticated manufacturing process is used to integrate DMOS and CMOS transistors into a single IC chip, then the integration capability is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor substrate into distinct transistor areas (DMOS transistor area and CMOS transistor area) using separation regions. This allows different transistor types to be fabricated in separate zones with area-specific ion implantation processes, enabling integration while managing process complexity through spatial division.
Solution Approach 2:
The patent employs preliminary action by forming separation regions and gate structures before performing ion implantation processes. The mask patterns are prepared in advance to define the areas for n-type and p-type well formation, allowing the manufacturing process to proceed systematically and reduce overall complexity.
2Adaptability or versatility
If a sophisticated manufacturing process is used to integrate DMOS and CMOS transistors into a single IC chip, then the integration capability is improved, but the manufacturing cost increases
Solution Approach 1:
By segmenting the substrate into distinct transistor areas and using area-specific ion implantation, the patent reduces the need for multiple separate fabrication lines. This approach allows integration of DMOS and CMOS transistors in a single manufacturing flow, thereby reducing overall manufacturing costs while maintaining integration capability.
Solution Approach 2:
The patent implements universality by using a common manufacturing process flow (ion implantation, mask patterns, separation regions) that serves multiple functions: forming both DMOS and CMOS transistors, creating well regions, and defining transistor areas. This multi-functional approach reduces the number of specialized processes needed, thereby lowering manufacturing costs.
3Manufacturing precision
If conventional methods with multiple mask patterns are used, then the manufacturing precision is maintained, but the productivity decreases
Solution Approach 1:
The patent applies preliminary action by forming separation regions and gate structures before ion implantation, and by preparing mask patterns in advance to define implantation areas. This preliminary preparation allows subsequent ion implantation processes to proceed efficiently without requiring multiple iterative masking steps, thereby maintaining precision while improving productivity.
Solution Approach 2:
The patent achieves continuity of useful action by using ion implantation processes that can simultaneously or sequentially form multiple well regions (n-type wells and p-type wells) in different transistor areas without interrupting the manufacturing flow. This continuous process reduces the number of discrete steps compared to conventional methods, thereby increasing productivity while maintaining fabrication precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the DMOS transistor fabrication process, reduces manufacturing costs, and shortens the production time while enabling the integration of DMOS and CMOS transistors into a single IC chip with improved reliability and performance.
Implementation Method 1
performing a first ion implantation process into the exposed second portion of the DMOS gate electrode and the semiconductor substrate to form n-type well (NWELL) regions
Implementation Method 2
forming separation regions in a semiconductor substrate, the separation regions isolating a DMOS transistor area from an NMOS transistor area and a PMOS transistor area
Data Source
AI summary
A method of fabricating a semiconductor device including a diffused metal-oxide-semiconductor (DMOS) transistor, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor includes forming separation regions in a semiconductor substrate, forming a gate insulating film, forming a DMOS gate electrode on the gate insulating film, forming a first mask pattern on the semiconductor substrate, performing a first ion implantation process, forming a second mask pattern on the semiconductor substrate, performing a second ion implantation process, forming a third mask pattern on the semiconductor substrate and performing a third ion implantation process into the semiconductor substrate, and forming a fourth mask pattern on the semiconductor substrate and performing a fourth ion implantation process.