DMOS Transistor Columnar Intermediate Region Depletion Layer Connection
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Solution Overview
Problem
The existing DMOS transistors experience a reduction in breakdown voltage due to non-connected depletion layers between adjacent transistors, particularly in regions far from the P-type base regions, leading to reduced current flow and increased resistance.
Innovation Solution
A semiconductor device with a columnar intermediate region and connection regions formed between the intermediate and base regions, ensuring depletion layers connect even in regions surrounded by multiple transistors, allowing the voltage to be applied directly to the depletion layers and not the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interval between DMOS transistors is spread to reduce resistance and enable larger current flow, then current carrying capacity is improved, but depletion layers become disconnected in regions surrounded by multiple transistors, causing breakdown voltage to reduce
Solution Approach 1:
An N-type intermediate region is introduced between adjacent P-type base regions to serve as a mediator that connects depletion layers from multiple transistors. This intermediate region enables continuous depletion layer formation across transistor boundaries, allowing both wide spacing for high current and connected depletion layers for high breakdown voltage.
2Power
If DMOS transistors are arranged side by side to allow large current flow vertically, then current flow capability is improved, but regions surrounded by multiple transistors create gaps where depletion layers cannot connect, reducing breakdown voltage
Solution Approach 1:
The base region is segmented into P-type base regions for each transistor and N-type intermediate regions positioned between them. This segmentation allows the depletion layers from adjacent P-type regions to connect through the N-type intermediate regions, solving the disconnection problem in multi-transistor surrounded areas while maintaining high current flow capability.
3Manufacturing precision
If the interval between transistors is increased to reduce resistance, then electrical resistance is reduced, but the depletion layer connection is lost in central regions, causing breakdown voltage to decrease
Solution Approach 1:
The N-type intermediate region acts as a mediator that bridges the gap between P-type base regions when transistors are spaced far apart. By providing this intermediate N-type region, depletion layers can continuously form from adjacent transistors through the intermediate region, maintaining high breakdown voltage even when transistor spacing is increased to reduce resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high breakdown voltage by ensuring depletion layers are connected across the semiconductor device, even in regions surrounded by multiple transistors, thereby enhancing current flow and reducing resistance.
Implementation Method 1
a reverse bias is applied to a PN junction between the P-type base region and the N-type semiconductor substrate due to the voltage applied between the source and drain electrodes, so that a depletion layer spreads
Implementation Method 2
ensuring depletion layers connect even in regions surrounded by multiple transistors, allowing the voltage to be applied directly to the depletion layers and not the gate insulating film
Data Source
AI summary
A semiconductor device includes field effect transistors, each having a semiconductor layer formed on a major surface of a semiconductor substrate, a base region formed in a surface layer portion of a semiconductor layer, a source region formed in a surface layer portion of the base region, a source electrode formed on the base region and the source region, a gate electrode formed on the semiconductor layer and the base region via a gate insulating film interposed therebetween, and a drain electrode formed on a back surface of the semiconductor substrate, and which are placed side by side. A columnar intermediate region is formed in its corresponding predetermined region of the surface layer portion of the semiconductor layer placed below each gate electrode. Connection regions are formed in the surface layer portion of the semiconductor layer to contact the intermediate region and the base regions.