DMOS FET Chip Scale Package Front-Side Electrode Design

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Solution Overview

Problem

Traditional DMOS FET semiconductor packages require connection using wires and clips, resulting in increased package size due to the vertical structure where the drain electrode is on the back side, hindering surface mount technology with high electrical resistance.

Innovation Solution

A semiconductor package with a metal-oxide-semiconductor field-effect transistor (MOSFET) where the source, gate, and drain electrodes are positioned on the front side, utilizing a redistribution layer and metal layer with partial drain plugs to facilitate a wafer level chip scale package (WLCSP) method, and grinding the back side to reduce package size and electrical resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the drain electrode is positioned on the back side in a vertical structure, then the traditional DMOS FET packaging can be implemented, but the package size increases and surface mount technology becomes difficult

Engineering Contradiction:

Improvepackage sizeVSAvoidsurface mount capability

Core Design Contradiction:

Volume of moving objectVSEase of operation

Solution Approach 1:

The patent inverts the traditional vertical structure by moving the drain electrode from the back side to the front side of the semiconductor device. This inversion allows all electrodes (source, gate, and drain) to be positioned on the front side, enabling surface mount technology and reducing package size by eliminating the need for wires and clips that connect back-side electrodes to the package substrate.

Inventive Principle:

Principle #13The other way round (Inversion)

2Reliability

If wires and clips are used for connection in traditional packaging, then the vertical structure is maintained, but the package size increases and electrical resistance increases

Engineering Contradiction:

Improveelectrical resistanceVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSVolume of moving object

Solution Approach 1:

The patent merges the electrode connections by positioning all electrodes (source, gate, and drain) on the front side of the semiconductor device. This merging eliminates the need for separate wires and clips that were previously required to connect back-side electrodes to the package substrate, thereby reducing package size and electrical resistance while improving reliability.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If the vertical structure with back-side drain electrode is used, then the traditional DMOS FET configuration is maintained, but the package complexity increases due to additional connection components

Engineering Contradiction:

Improvepackage structureVSAvoidmanufacturing simplicity

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The patent inverts the traditional vertical structure to position the drain electrode on the front side, thereby eliminating the need for wires and clips. This structural inversion simplifies the package design by reducing the number of components and connection steps, making the manufacturing process more straightforward and less complex.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS11699627B2DMOS FET chip scale package and method of making the same

Publication Date: 2023.07.11 ALPHA & OMEGA SEMICON INT LP

AI summary

A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.