DMOS Device Sealed Channel Processing for Planar Surface
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Solution Overview
Problem
Existing semiconductor fabrication methods for MOS transistors result in non-planar surfaces and increased parasitic resistance due to silicon steps in the channel region, degrading electrical properties and requiring additional processing steps.
Innovation Solution
A method involving the formation of a silicon nitride layer to limit oxygen diffusion and prevent silicon consumption, ensuring a planar surface and reducing parasitic resistance by using a pad oxide layer, silicon nitride layer, and top oxide layer to align dopant regions and control annealing, thereby eliminating silicon steps and enhancing channel surface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal annealing is performed to drive-in dopants, then dopant diffusion is improved, but oxygen diffuses to the silicon surface causing non-planar surface and silicon steps
Solution Approach 1:
A silicon nitride sealing layer is introduced as an intermediary barrier between the oxygen-containing environment and the silicon surface. This layer prevents oxygen from reaching the silicon during thermal annealing, thereby maintaining surface planarity while allowing dopant diffusion to proceed through the silicon bulk
Solution Approach 2:
The oxide layer is segmented into two parts: a bottom oxide layer that remains to prevent dopant diffusion, and a top oxide layer that is removed to expose the planar silicon surface. This segmentation allows selective control over dopant regions while maintaining overall surface planarity
2Reliability
If LDD regions are added to increase breakdown voltage, then device reliability is improved, but parasitic resistance increases and switching speed degrades
Solution Approach 1:
The doping concentration parameters are precisely controlled through selective drive-in processes. By adjusting annealing temperature, time, and oxygen partial pressure, the invention achieves adequate breakdown voltage with minimized LDD region doping, thereby reducing parasitic resistance and improving switching speed
3Productivity
If channel region size is reduced to increase drive current, then device functionality is improved, but manufacturing precision becomes more difficult to control
Solution Approach 1:
The silicon nitride sealing layer provides self-aligned protection during thermal processing. The layer is deposited conformally and removed selectively, automatically defining the channel region boundaries without requiring additional alignment steps, thereby maintaining precise channel dimensions even at scaled sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively eliminates silicon steps, improves channel surface quality, reduces parasitic resistance, and enhances electrical properties of MOS devices by maintaining a continuous and planar surface, leading to superior carrier mobility and device reliability.
Implementation Method 1
the diffusion of oxygen to the surface of the substrate during the annealing step is limited by the silicon nitride layer
Implementation Method 2
A first dopant region is then formed (i.e., by diffusion or implantation) in a first portion of the substrate
Data Source
AI summary
A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.