DMOS Transistor Source-Substrate Punch-Through Mitigation
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Solution Overview
Problem
DMOS-transistors in CMOS processes face limitations in source-substrate electric strength due to the punch-through effect, which restricts their applications, and existing solutions require additional process steps increasing costs and altering other characteristics.
Innovation Solution
A DMOS-transistor structure is enhanced by incorporating a highly doped region with complementary doping in a second well, positioned below the source region, to increase the source-substrate punch-through voltage without affecting the drain break-through voltage, using existing CMOS process steps to maintain compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If additional process steps are implemented in the CMOS process flow to suppress punch-through effects, then the electric strength is improved, but the manufacturing complexity and costs increase
Solution Approach 1:
The patent merges the formation of the highly doped region beneath the source with existing CMOS well formation process steps. By integrating this additional doping step into the standard well creation sequence, the solution improves electric strength without requiring separate, complex additional process flows, thereby maintaining manufacturing simplicity and cost-effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the electric strength of the source-substrate path while maintaining the drain's electric strength, achieved through CMOS-compatible processes without modifying existing steps, resulting in enhanced performance in automotive CMOS processes with increased voltage capabilities.
Implementation Method 1
the electric strength is limited by the punch-through effect that will then be effective
Implementation Method 2
In particular avalanche effects should be reduced by incorporating an additional p-well (buried p-type body)
Data Source
AI summary
A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the first well region. A gate electrode and a gate insulation layer for forming a transistor channel are included on a surface of the first well region. The DMOS-transistor further comprises an isolation structure, a highly doped drain doping region, and a second well complementarily doped to the first well region. The second well accommodates the first well region and the drain doping region. A highly doped region is formed at least adjacent to the second well and has the same type of doping as the second well for enhancing the dielectric strength of the highly doped source region.