DMOS Termination Wiring Layout for Withstand Voltage Stability
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Solution Overview
Problem
The semiconductor device with a DMOS transistor experiences a decrease in withstand voltage due to the influence of potentials from other wirings, which disturbs the equipotential distribution and reduces the transistor's voltage tolerance.
Innovation Solution
A conductive wiring is disposed on the peripheral edge of the element region, extending into the element termination region and covering part of the area between the n-type drain contact region and the p-type element isolation region, ensuring electrical connection and enhancing voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If other wirings are formed in the semiconductor device to connect other elements, then the device functionality is improved, but the withstand voltage of the DMOS transistor decreases due to potential influence from these other wirings
Solution Approach 1:
A conductive wiring is disposed on the peripheral edge portion of the element region to create an equipotential region that covers at least part of the element termination region. This equipotential conductive wiring prevents potential differences caused by other wirings from affecting the DMOS transistor's withstand voltage, while allowing other elements and wirings to be freely configured in the device.
2Reliability
If the conductive wiring is extended into the element termination region to suppress withstand voltage decrease, then the voltage stability is improved, but the device structure becomes more complex
Solution Approach 1:
The conductive wiring serves multiple functions: it acts as an equipotential region to suppress withstand voltage decrease, functions as a drain wiring to electrically connect to the n-type drain contact region, and can be configured to extend into the element termination region. By making the conductive wiring multi-functional, the patent avoids adding separate structures, thereby reducing overall device complexity while achieving voltage stability.
Data Source
AI summary
A semiconductor device 1 includes a base body 3 that includes a p type substrate 4 and an n type semiconductor layer 5 formed on the p type substrate 4 and includes an element region 2 having a transistor 40 with the n type semiconductor layer as a drain, a p type element isolation region 7 that is formed in a surface layer portion of the base body such as to demarcate the element region, and a conductive wiring 25 that is disposed on a peripheral edge portion of the element region and is electrically connected to the n type semiconductor layer. The transistor includes an n+ type drain contact region 14 that is formed in a surface layer portion of the n type semiconductor layer in the peripheral edge portion of the element region. The conductive wiring is disposed such as to cover at least a portion of an element termination region 30 between the n+ type drain contact region and the p type element isolation region.