Monolithic DMOS Transistor Using Epi Extension Diffusion
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Solution Overview
Problem
Existing monolithic integrated circuits face challenges in building high voltage DMOS transistors due to thin epitaxy layers, which lead to punch-through issues and increased chip area, making it difficult to create economical circuits with both high and low voltage components on the same chip.
Innovation Solution
A high voltage, high side lateral DMOS transistor is developed using an epi extension diffusion and a five-layer RESURF structure with alternately doped layers, including a p-type substrate, n-type epi extension diffusion, p-type buried layer, n-type epi, and shallow p-type layer, to avoid punch-through and reduce specific R_on by providing an alternate path for drain current and optimizing electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick epitaxy layer is used to support high voltage, then breakdown voltage is improved, but chip area increases due to wide isolation diffusion
Solution Approach 1:
The isolation structure is segmented into multiple regions: deep isolation diffusion regions extending halfway through the epitaxy layer, and shallow isolation diffusion regions at the surface. This segmentation allows the deep regions to provide voltage support while shallow regions minimize lateral diffusion and chip area occupation.
Solution Approach 2:
Different regions of the chip have different isolation depths tailored to their specific needs. High voltage regions use deep isolation diffusions for voltage support, while low voltage regions use shallow isolations to minimize area. The alternately doped layers also create local quality variations with different doping concentrations in drift regions versus channel regions.
2Area of stationary object
If traditional monolithic process with thin epi is used, then chip area is reduced, but punch-through occurs at low voltage
Solution Approach 1:
Deep isolation diffusion regions are formed in advance, extending halfway through the epitaxy layer before the active device layers are formed. This preliminary action creates a foundation that supports high voltage breakdown while allowing the rest of the device to be built on a thinner effective epitaxy layer, preventing punch-through.
Solution Approach 2:
The isolation structure uses a nested configuration where shallow isolation diffusions are positioned above and within the lateral extent of deeper isolation diffusions. This nested arrangement allows the deep isolations to provide voltage support from the substrate while shallow isolations provide surface-level isolation, achieving both voltage support and area efficiency.
3Strength
If deep isolation diffusion is used to support high voltage, then breakdown voltage is improved, but lateral diffusion increases occupying large area
Solution Approach 1:
The isolation function is segmented between deep isolation diffusions that extend vertically halfway through the epitaxy for voltage support, and shallow isolation diffusions that remain at the surface level to minimize lateral area occupation. This segmentation allows each layer to perform its specific function optimally.
Solution Approach 2:
The isolation structure transitions from a purely lateral two-dimensional expansion to a three-dimensional vertical structure. Deep isolation diffusions extend in the vertical dimension halfway through the epitaxy layer, providing voltage support without requiring proportional lateral area expansion. The shallow isolations maintain compact lateral footprints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of high voltage DMOS transistors that can be part of a low voltage BCD process, reducing chip area and specific R_on by nearly 50% while maintaining high breakdown voltage, allowing for efficient monolithic integration of high and low voltage components.
Implementation Method 1
a five-layer RESURF structure with alternately doped layers, including a p-type substrate, n-type epi extension diffusion, p-type buried layer, n-type epi, and shallow p-type layer, to avoid punch-through and reduce specific R_on by providing an alternate path for drain current and optimizing electric field distribution
Implementation Method 2
epi extension diffusion and a five-layer RESURF structure with alternately doped layers... to provide an alternate path for drain current
Data Source
AI summary
A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon.