DMOS Transistor ESD Protection via Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor protection circuits face challenges in effectively protecting high-voltage terminals from Electro-Static Discharge (ESD) due to inadequate capacitive coupling, which can lead to degraded functionality and increased manufacturing complexity.
Innovation Solution
The use of DMOS transistors with innovative parasitic capacitance configurations, including pn-junction and MOS capacitances, to enhance capacitive coupling and ensure reliable ESD protection without the need for additional capacitive elements, thereby reducing manufacturing steps and improving area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only gate-drain parasitic capacitance of MOS is used as capacitive element, then the protection circuit structure is simple, but capacitive coupling is insufficient and gate-source voltage cannot be sufficiently secured
Solution Approach 1:
The patent combines gate-drain parasitic capacitance and gate-source parasitic capacitance of the MOS transistor to form a composite capacitive element. This merging of two parasitic capacitances provides sufficient capacitive coupling for ESD protection while maintaining circuit simplicity and avoiding additional manufacturing steps.
2Reliability
If oxide film capacitance is used by thickening gate oxide film, then high breakdown voltage is achieved, but the number of manufacturing steps increases
Solution Approach 1:
The patent utilizes the inherent parasitic capacitances that already exist in the MOS transistor structure without requiring additional manufacturing steps. The gate-drain and gate-source parasitic capacitances are naturally formed during standard MOS fabrication, allowing the circuit to serve its own capacitive function without external assistance or additional processing.
3Reliability
If pn-junction capacitance is used, then high breakdown voltage is achieved, but area efficiency deteriorates and cost increases
Solution Approach 1:
The MOS transistor serves multiple functions simultaneously: it acts as the protection switch, provides capacitive coupling through its parasitic capacitances, and offers high breakdown voltage capability. This multi-functionality eliminates the need for separate capacitive elements that would occupy additional area, making the transistor a universal component for ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively turns on transistors to manage surge currents, providing robust ESD protection for high-voltage terminals while minimizing process complexity and maintaining high breakdown voltages, thus preventing erroneous writes in anti-fuse elements and ensuring reliable operation.
Implementation Method 1
voltage fluctuations in a voltage line is transmitted to the gate of a transistor M1 via a gate-drain parasitic capacitance of the transistor M1
Implementation Method 2
gate-drain parasitic capacitance of the transistor M1
Implementation Method 3
a current flows from the voltage line to the ground line, discharging the surge voltage in the voltage line
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.