DMOS Transistor Gated Channel for Breakdown Voltage
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Solution Overview
Problem
Conventional DMOS transistors face challenges in achieving increased breakdown voltage while avoiding damage to the gate dielectric material and undesirable dopant diffusion, which can lead to early breakdown and punch-through issues during switching off.
Innovation Solution
The implementation of an additional implantation into the channel region of the DMOS transistor to form a doped channel region, with the implantation performed before forming the gate dielectric material, and using a gapped gate electrode structure to enable increased lateral diffusion of well dopants without vertical extension, thereby enhancing channel length and compensating for punch-through voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If additional doping is performed into the channel region to create a conductive path for depletion mode operation, then the transistor can conduct at zero gate voltage, but this causes early breakdown and punch-through issues when switching off
Solution Approach 1:
The channel region is divided into two distinct doped regions: a first doped channel region with higher dopant concentration for conductivity at zero gate voltage, and a second doped channel region with lower dopant concentration to prevent punch-through during switching off. This segmentation allows each region to fulfill different functional requirements simultaneously.
Solution Approach 2:
Different dopant concentrations are applied to different portions of the channel region. The first doped channel region has increased dopant concentration to ensure conductivity at zero gate voltage, while the second doped channel region has reduced dopant concentration to extend the depletion length and prevent punch-through, creating local quality variations to optimize both conductivity and breakdown characteristics.
2Reliability
If the channel length is increased to prevent punch-through, then breakdown voltage improves, but this increases device area and affects switching speed
Solution Approach 1:
The dopant concentration is varied locally along the channel length. The second doped channel region has lower dopant concentration specifically in the portion farthest from the source, which extends the depletion length to prevent punch-through without requiring a physically longer channel, thereby maintaining switching speed while improving breakdown voltage.
3Ease of manufacture
If conventional implantation methods are used to dope the channel region, then additional doping can be achieved, but this damages the gate dielectric material
Solution Approach 1:
The additional doping of the channel region is performed before forming the gate dielectric layer. This preliminary action allows the dopant to be incorporated into the semiconductor substrate without requiring implantation through the gate dielectric, thereby avoiding damage to the gate dielectric material while still achieving the desired doped channel region for depletion mode operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the breakdown voltage and prevents early punch-through, maintaining transistor performance while avoiding damage to the gate dielectric and reducing vertical dopant diffusion.
Implementation Method 1
The channel region (9) of the DMOS transistor (10) receives an additional implantation into the channel region (9) so as to form a doped channel region (21)
Implementation Method 2
using a gapped gate electrode structure to enable increased lateral diffusion of well dopants without vertical extension
Data Source
AI summary
A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.