DMOS Transistor Silicide Layer Design for ESD Strength
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DMOS transistors face challenges in reducing ON resistance while maintaining strength against electrostatic discharge, as silicide layers can cause electric field convergence and deterioration in discharge strength due to their low resistance.
Innovation Solution
A DMOS transistor structure is designed with a silicide layer on the source layer but not between the source layer and the gate electrode, and a silicidation prevention film is used to prevent the silicide layer from forming on the body layer between the source and gate, ensuring the electric field is relaxed and current flows uniformly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicide layer is formed on the source layer to reduce ON resistance, then the ON resistance decreases, but the strength against electrostatic discharge deteriorates due to electric field convergence
Solution Approach 1:
The patent applies local quality by forming the silicide layer selectively only on specific regions of the source layer (the region not overlapping with the gate electrode in plan view), while intentionally leaving other regions without silicide layer. This localized differentiation allows the silicide to reduce ON resistance in appropriate areas while avoiding electric field convergence at critical regions near the gate electrode, thus resolving the contradiction between low ON resistance and high electrostatic discharge strength.
2Reliability
If the silicide layer is formed on the source layer surface, then current conduction improves, but electric field convergence occurs at the edge portion causing deterioration in discharge strength
Solution Approach 1:
The patent segments the source layer surface into distinct regions: one region where the silicide layer is formed (for improved current conduction) and another region where the silicide layer is not formed (to avoid electric field convergence). This segmentation is achieved by controlling the silicide formation process to exclude areas overlapping with the gate electrode in plan view, thereby separating the functions of current conduction and electric field management into different spatial zones.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure effectively reduces ON resistance and enhances the transistor's strength against electrostatic discharge by preventing electric field convergence and ensuring uniform current flow.
Implementation Method 1
forming a silicide layer, which is a product of reaction between silicon and a transition metal such as cobalt or titanium, on a surface of a source layer
Implementation Method 2
the electric field at the edge portion of the source layer is relaxed and the convergence of the electric current is not likely to occur
Data Source
AI summary
This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.