Reduced Electric Field DMOS via Self-Aligned Trench Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing electric fields and parasitic capacitance due to the presence of gate wrap-around regions, which degrade performance and increase fabrication complexity.
Innovation Solution
The implementation of shallow trench isolation with a trench-fill dielectric that maintains full-field oxide thickness, eliminating the gate wrap-around region by using a silicon nitride layer with a high selectivity etchant and planarizing the dielectric layers to reduce electric fields and capacitance between the gate and drift regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional MOS transistor fabrication with LDD regions is used, then breakdown voltage is improved, but parasitic resistance increases and switching speed degrades
Solution Approach 1:
The patent extracts and eliminates the LDD region from the device structure, using a different approach (self-aligned trench isolation with retrograde well) to achieve both high breakdown voltage and low parasitic resistance simultaneously, rather than accepting the trade-off imposed by LDD regions
Solution Approach 2:
The patent changes the doping profile parameters by implementing a retrograde well structure with peak doping concentration deeper in the substrate, which allows high breakdown voltage without the parasitic resistance penalty of LDD regions
2Ease of manufacture
If gate wrap-around region is present in trench isolation, then fabrication is simplified, but electric field concentration increases and device reliability decreases
Solution Approach 1:
The patent performs preliminary planarization of the trench isolation structure before gate deposition, eliminating the wrap-around geometry in advance and preventing electric field concentration at the gate-drift region interface
Solution Approach 2:
The patent uses planarized (flat) trench isolation surfaces instead of curved or sloped surfaces, eliminating the geometric concentration of electric fields that occurs at curved interfaces
3Productivity
If channel region size is reduced to increase device density, then integration density is improved, but channel control and breakdown voltage become more difficult to maintain
Solution Approach 1:
The patent moves the doping peak from the surface plane to a deeper vertical dimension (retrograde well with peak at 0.5-2.0 micrometers depth), allowing short surface channels for high density while maintaining breakdown voltage through deep substrate doping
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances isolation voltage and reduces capacitance, minimizing local electric fields and maintaining carrier trajectory, thereby improving device performance without adding complexity to the fabrication process.
Implementation Method 1
forming a first silicon nitride layer over the first silicon dioxide layer. The first nitride layer is chosen since a high selectivity ratio etchant can be used in later processing steps to etch the nitride at a different rate from the silicon dioxide layer
Implementation Method 2
The dielectric layer (i.e., the trench-fill) is planarized to be substantially coplanar with an uppermost surface of the nitride layer
Data Source
AI summary
A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.