DMOS Transistor Well Layer Voltage Isolation Chip Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing DMOS transistor technology limits the integration of multiple device elements within a single region due to voltage differences across confined areas, necessitating multiple confined regions and increasing chip area, while also failing to achieve low on resistance and high electric current driving capacity.
Innovation Solution
A semiconductor device with a well layer of a second conductivity type separates elements, featuring a DMOS transistor with a body layer, source, gate electrode, and drain layer, and a first diffusion layer to reduce on resistance, allowing for efficient voltage isolation and high current driving capacity within a single confined region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple confined regions are formed to accommodate different voltage requirements, then device functionality is achieved, but chip area increases
Solution Approach 1:
The patent merges multiple confined regions into a single confined region by introducing a well layer that electrically isolates different voltage domains. This allows DMOS transistors (high voltage) and P channel MOS transistors (low voltage) to coexist in the same confined region without electrical interference, thereby reducing chip area while maintaining voltage compatibility.
Solution Approach 2:
The well layer acts as an intermediary structure between the semiconductor substrate and the epitaxial layer, providing electrical isolation and potential fixation. This intermediary enables different voltage domains to share a common confined region by preventing voltage interference between high voltage and low voltage devices.
2Device complexity
If the epitaxial layer serves as the drain region, then device simplicity is maintained, but integration of multiple device elements is limited
Solution Approach 1:
The patent segments the drain region into two parts: the epitaxial layer serves as one drain region for the DMOS transistor, while the well layer forms a separate drain region for the P channel MOS transistor. This segmentation allows multiple device elements to be integrated within a single confined region while maintaining the simplicity of using the epitaxial layer as a drain region for high voltage devices.
3Reliability
If multiple confined regions are used for different voltage domains, then voltage isolation is achieved, but manufacturing complexity increases
Solution Approach 1:
The well layer serves multiple functions simultaneously: it acts as a drain region for P channel MOS transistors, provides voltage isolation between high and low voltage domains, fixes the potential of the body layer, and enables the formation of multiple device elements within a single confined region. This multi-functionality achieves voltage isolation without increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces chip area by enabling multiple device elements to share a single region, achieving low on resistance and high electric current driving capacity while maintaining high source-drain breakdown voltage.
Implementation Method 1
a first diffusion layer of a first conductivity type for reducing on resistance
Data Source
AI summary
It is desirable to reduce chip area, lower on resistance and improve electric current driving capacity of a DMOS transistor in a semiconductor device with a DMOS transistor. On the surface of an N type epitaxial layer, a P+W layer of the opposite conductivity type (P type) is disposed and a DMOS transistor is formed in the P+W layer. The epitaxial layer and a drain region are insulated by the P+W layer. Therefore, it is possible to form both the DMOS transistor and other device element in a single confined region surrounded by an isolation layer. An N type FN layer is disposed on the surface region of the P+W layer beneath the gate electrode. An N+D layer, which is adjacent to the edge of the gate electrode of the drain layer side, is also formed. P type impurity layers (a P+D layer and a FP layer), which are located below the drain layer, are disposed beneath the contact region of the drain layer.