Bidirectional Memory Synchronize Engine for FPGA Data Latency
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Solution Overview
Problem
Current methods for data synchronization between a host side and an FPGA accelerator suffer from high latency and reduced system throughput, particularly in applications like AI reasoning, due to the need for software-instruction-based passive memory copying and additional steps for data migration.
Innovation Solution
A method involving a Bidirectional Memory Synchronize Engine (DMSE) that uses state information in two address spaces to establish and maintain a reliable memory synchronization communication link, allowing DMA to migrate data efficiently between the host and FPGA accelerators, thereby reducing latency and improving throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-instruction-based passive memory copying method is used, then data migration can be controlled through instructions, but data synchronization latency increases and system throughput efficiency decreases
Solution Approach 1:
The patent replaces software-instruction-based control with a hardware-based Bidirectional Memory Synchronization Engine (BMSE) that automatically manages data synchronization between host memory and FPGA accelerator memory. The BMSE uses hardware logic to detect data frame numbers, determine synchronization status, and trigger DMA transfers without software intervention, thereby reducing latency while maintaining reliability
Solution Approach 2:
The BMSE implements self-service by autonomously monitoring data frame numbers in both host and FPGA memories, automatically determining whether synchronization is needed, and triggering DMA transfers without requiring software instructions. The engine services itself by managing its own control registers and state machine, eliminating the need for software control loops
2Reliability
If additional steps for data synchronization are implemented, then data consistency between host and FPGA is maintained, but processing pressure on host side increases
Solution Approach 1:
The patent extracts the data synchronization functionality from the host CPU by implementing a standalone BMSE in the FPGA. The BMSE independently handles all synchronization operations including reading data frame numbers, comparing states, and triggering DMA transfers, thereby removing the processing burden from the host while maintaining data consistency
Solution Approach 2:
The BMSE acts as an intermediary between host memory and FPGA memory, managing all synchronization operations. It uses control registers in the Bar space to communicate synchronization status and triggers DMA transfers autonomously, freeing the host from direct involvement in synchronization while ensuring data consistency through its state machine logic
3Productivity
If DMA-based active memory copying is used, then data migration speed increases, but synchronization control complexity increases
Solution Approach 1:
The BMSE performs preliminary actions by continuously monitoring data frame numbers in both host and FPGA memories and maintaining a state machine that is ready to trigger DMA transfers. The engine pre-establishes the synchronization logic and control registers in the Bar space, so when data needs synchronization, the DMA transfer can be initiated immediately without complex runtime control
Data Source
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AI summary
Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202). It can be seen that, according to the method, a data synchronization operation is implemented based on state information in two address spaces, and double-end memory data synchronization is performed by a controller at the side of the FPGA accelerator. Therefore, the data synchronization latency is reduced, and the system throughput is improved.