Decoder Motion Vector Refinement Latency Reduction
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Solution Overview
Problem
Current video coding technologies face challenges in reducing latency during decoder-side motion vector derivation, which affects the efficiency of video decoding and compression.
Innovation Solution
The implementation of decoder-side motion vector refinement (DMVR) and bi-directional optical flow (BDOF) processes, which determine the usage of these processes based on the status of other DMVD processes, enabling or disabling them to reduce complexity and latency in inter prediction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If decoder-side motion vector refinement (DMVR) and bi-directional optical flow (BDOF) processes are implemented, then motion vector derivation accuracy is improved, but computational complexity and latency increase
Solution Approach 1:
The patent implements dynamic selection of DMVR and BDOF processes based on prediction mode, block size, and motion complexity. The decoder adaptively enables or disables these computationally intensive processes for different blocks, allowing high accuracy when needed while reducing complexity for simpler cases, thus resolving the contradiction between precision and computational load
Solution Approach 2:
The patent changes the operational parameters of the decoding process by introducing conditional execution of DMVR and BDOF based on multiple criteria including prediction mode flags, block dimensions, and motion vector differences. This parameter-based control allows the system to optimize between accuracy and complexity on a per-block basis
2Measurement precision
If decoder-side motion vector refinement (DMVR) and bi-directional optical flow (BDOF) processes are implemented, then motion vector derivation accuracy is improved, but decoding latency increases
Solution Approach 1:
The patent dynamically controls the execution of DMVR and BDOF processes based on real-time assessment of block characteristics and motion complexity. By enabling these processes only when necessary and disabling them for simple blocks, the system reduces average decoding latency while maintaining high accuracy for complex regions, thus resolving the precision-latency tradeoff
Solution Approach 2:
The patent applies partial action by selectively applying DMVR and BDOF to only those blocks that require enhanced motion vector accuracy, rather than applying these processes uniformly to all blocks. This selective approach reduces overall decoding latency while maintaining high precision where needed
3Measurement precision
If multiple DMVD processes are used on the current block, then prediction accuracy is improved, but processing complexity increases
Solution Approach 1:
The patent implements dynamic selection among multiple DMVD processes (DMVR, BDOF, and their combinations) based on prediction mode, block characteristics, and motion complexity. The decoder adaptively chooses the appropriate process or combination for each block, achieving high prediction accuracy when needed while minimizing processing complexity for simpler cases
Solution Approach 2:
The patent segments the video picture into multiple blocks and applies different DMVD processes to different segments based on their characteristics. This block-level segmentation allows the system to use multiple complex processes only where necessary, achieving high overall prediction accuracy while managing processing complexity through localized application of advanced techniques
Data Source
AI summary
Methods and apparatuses for video encoding/decoding are provided. In some examples, an apparatus for video decoding includes receiving circuitry and processing circuitry. The processing circuitry decodes prediction information of a current block in a current picture from a coded video bitstream. The prediction information is indicative of an inter prediction mode. Then, the processing circuitry determines a usage of a first DMVD process on the current block at least partially based on a second DMVD process not being used on the current block. Further, the processing circuitry reconstructs the current block according to the inter prediction mode with the first DMVD process.