Acceleration Chip Intermediate Value Storage for DNN Energy Reduction
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Solution Overview
Problem
Current neural network algorithms face high energy consumption and data processing issues due to frequent storage and retrieval of intermediate values in primary memory, which increases power usage and can lead to data missing and replacement problems.
Innovation Solution
An acceleration chip with a vector addition processor module, vector function value arithmetic unit module, and vector multiplier-adder module, equipped with intermediate value storage regions, reduces memory access by discarding intermediate values after output generation and using random-access memory to store and manage these values efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If intermediate values are stored in primary memory using general processor method, then data can be preserved, but space of primary memory is increased and power consumption is increased
Solution Approach 1:
The patent segments the memory system into two parts: primary memory for permanent storage and intermediate value storage regions within functional modules for temporary storage. This segmentation allows intermediate values to be kept in fast, low-power local storage rather than repeatedly accessing high-power primary memory, reducing overall power consumption while maintaining data availability.
Solution Approach 2:
The intermediate value storage regions act as intermediary buffers between functional modules and primary memory. By introducing these intermediary storage areas, the system reduces the frequency of primary memory accesses, thereby lowering power consumption while ensuring that intermediate values are preserved when needed.
2Reliability
If intermediate values are stored in primary memory, then data can be preserved, but number of read/write operations to primary memory is increased
Solution Approach 1:
By segmenting storage into primary memory and local intermediate value storage regions, the patent enables functional modules to access intermediate values locally without repeatedly reading from and writing to primary memory. This reduces the number of I/O operations and improves processing efficiency.
Solution Approach 2:
The patent implements preliminary action by pre-allocating intermediate value storage regions within functional modules. These regions are prepared in advance to hold intermediate values, eliminating the need for frequent primary memory accesses during processing and thereby improving operational efficiency.
3Ease of manufacture
If general processor is used for neural network algorithm, then implementation is simple, but performance to power ratio is low
Solution Approach 1:
The patent implements a dynamic heterogeneous multi-core processor framework that can adaptively allocate tasks between different processing units based on their capabilities and current workload. This dynamic approach optimizes the performance-to-power ratio by using specialized units for computationally intensive neural network operations while maintaining the simplicity of general processor control.
Solution Approach 2:
The patent changes the operational parameters of the processing system by introducing specialized functional modules with dedicated intermediate value storage. This parameter change enables more efficient data processing with reduced memory access requirements, thereby improving the performance-to-power ratio while keeping the overall system architecture relatively simple.
Data Source
AI summary
The present disclosure provides an operation apparatus and method for an acceleration chip for accelerating a deep neural network algorithm. The apparatus comprises: a vector addition processor module and a vector function value arithmetic unit and a vector multiplier-adder module wherein the three modules execute a programmable instruction, and interact with each other to calculate values of neurons and a network output result of a neural network, and a variation amount of a synaptic weight representing the interaction strength of the neurons on an input layer to the neurons on an output layer; and the three modules are all provided with an intermediate value storage region and perform read and write operations on a primary memory.