DNN Accelerator Channel-Separable Operations
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Solution Overview
Problem
Deep neural networks (DNNs) face challenges in energy efficiency due to high computing demands, particularly in edge applications where silicon area and leakage power are concerns, and existing techniques for depthwise convolution underutilize MACs and require separate hardware, leading to inefficiencies in processing channel-separable operations.
Innovation Solution
A DNN accelerator design that includes a memory, processing element assembly, and controlling module to facilitate data reuse during depthwise convolutions, allowing the same compute unit to handle both standard and depthwise convolutions, reducing data read accesses and optimizing silicon area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate hardware is used for depthwise convolution, then processing capability is improved, but device complexity and silicon area increase
Solution Approach 1:
The patent implements a unified processing element assembly that can perform both standard convolution and depthwise convolution operations. The processing elements are designed with flexible functionality to handle different convolution types without requiring separate dedicated hardware, thereby reducing device complexity while maintaining processing capability for both operation types
2Reliability
If data is read multiple times for depthwise convolution, then processing accuracy is maintained, but energy consumption increases
Solution Approach 1:
The patent implements a buffer memory structure that pre-loads and stores input data before the depthwise convolution operation. This preliminary action allows the processing elements to access stored data multiple times without repeated reads from external memory, maintaining processing accuracy while significantly reducing energy consumption associated with data access
3Measurement precision
If MAC operations are performed for each input, then computing accuracy is improved, but productivity decreases
Solution Approach 1:
The patent implements a continuous processing architecture where processing elements perform MAC operations in a streamlined sequence without interruption. The design enables continuous data flow and computation, maintaining computing accuracy through proper accumulation while improving productivity by eliminating idle cycles and optimizing the operational continuity of the processing elements
4Productivity
If silicon area is increased for DNN accelerator, then processing capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent designs processing elements with multi-functional capability to handle both standard and depthwise convolutions, reducing the overall silicon area required. This universal design approach maintains processing capability while minimizing manufacturing costs by avoiding duplication of dedicated hardware for different operation types
Data Source
AI summary
An DNN accelerator includes a column of PEs and an external adder assembly for performing depthwise convolution. Each PE includes register files, multipliers, and an internal adder assembly. Each register file can store an operand (input operand, weight operand, etc.) of the depthwise convolution. The operand includes a sequence of elements, each of which corresponds to a different depthwise channel. A multiplier can perform a sequence of multiplications on two operands, e.g., an input operand and a weight operand, and generate a product operand. The internal adder assembly can accumulate product operands and generate an output operand of the PE. The output operand includes output elements, each of which corresponds to a different depthwise channel. The operands may be reused in different rounds of operations by the multipliers. The external adder assembly can accumulate output operands of multiple PEs and generate an output operand of the PE column.