Multi-Voltage DNN Accelerator Using SRAM Leakage Reuse
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Solution Overview
Problem
Existing DNN accelerators face challenges in energy efficiency due to high leakage energy loss from large on-chip memory and inefficient power management, particularly in monolithic architectures that lack flexibility for diverse DNN models and models with varying computational requirements.
Innovation Solution
Implementing a multi-voltage domain heterogeneous DNN accelerator architecture with near-memory computing through leakage reuse, where idle SRAM banks supply current to active computing units, optimizing power delivery and reducing leakage energy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large on-chip memory is used to reduce data movement latency and energy, then data access performance is improved, but leakage energy loss increases significantly
Solution Approach 1:
The patent divides the monolithic PE array into multiple subarrays with independent power domains, allowing selective activation of memory blocks based on computational needs. This segmentation enables the system to activate only the necessary portion of on-chip memory rather than the entire memory array, reducing leakage energy loss while maintaining fast data access for active computations.
Solution Approach 2:
The patent implements dynamic voltage scaling and power domain management where different subarrays can operate at different voltages and power states. The system dynamically adjusts power supply to memory blocks based on actual computational requirements, transitioning between active and idle states to minimize leakage energy while preserving data access performance when needed.
2Device complexity
If monolithic architecture is used for simplicity, then device complexity is reduced, but adaptability to diverse DNN models is limited
Solution Approach 1:
The patent segments the uniform PE array into heterogeneous subarrays with different computational capabilities and power domains. This allows the architecture to adapt to diverse DNN models by activating only the necessary subarrays for specific computational tasks, providing model adaptability while maintaining a relatively simple base architecture that can be configured differently.
Solution Approach 2:
The patent creates a universal accelerator architecture where the same PE array can serve multiple functions by dynamically configuring which subarrays are active and at what power levels. The heterogeneous subarrays can be activated based on the specific DNN model being executed, allowing a single device to efficiently handle diverse workloads from simple to complex models.
3Device complexity
If single voltage domain is used for simplicity, then power management complexity is reduced, but energy efficiency for diverse computational requirements is compromised
Solution Approach 1:
The patent divides the PE array into multiple subarrays, each with its own independent power domain. This segmentation allows different subarrays to operate at different voltages simultaneously, optimizing energy efficiency by applying higher voltage only to subarrays performing computationally intensive operations while maintaining lower voltage for less demanding subarrays, thereby reducing overall power consumption.
Solution Approach 2:
The patent implements local quality control where each subarray can be independently powered at its optimal voltage level based on local computational requirements. This allows fine-grained power management where only the necessary portion of the array consumes high power, while the rest operate at lower power levels, significantly improving overall energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed architecture significantly improves energy efficiency by recycling leakage current, achieving up to 71.4 times higher energy efficiency and reducing power consumption by 0.31-2.38 W, making it suitable for diverse DNN models and edge devices.
Implementation Method 1
The leakage current from idle on-chip storage (SRAM) is reused to deliver power to the computing units within the processing elements
Data Source
AI summary
A multi-voltage domain heterogeneous deep neural network (DNN) accelerator architecture includes an architecture that a) executes multiple DNN models simultaneously with different power-performance operating points; and b) improves the energy efficiency of near-memory computing applications by recycling leakage current of idle memories. The multi-voltage heterogenous DNN architecture may be implemented on battery operated or battery less edge devices with on-device intelligence executing applications including computer vision, augmented/virtual reality, face recognition, image processing, and speech applications.