DNN Fixed-Point Precision Selection for Low-Power Hardware

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Solution Overview

Problem

Existing hardware implementations of Deep Neural Networks (DNNs) face challenges in efficiently utilizing resources such as silicon area and processing power, and require flexibility to support various DNN configurations.

Innovation Solution

A hierarchical method for selecting fixed point number formats with reduced mantissa bit lengths is applied to DNN layers, iteratively adjusting these formats in subsets until an error threshold is reached, and forming disjoint subsets as necessary to optimize mantissa bit lengths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If fixed point number formats with reduced mantissa bit lengths are used, then power consumption and silicon area are reduced, but output error increases

Engineering Contradiction:
Improvepower consumptionVSAvoidoutput error
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent changes the parameters of fixed point number formats (mantissa bit length, exponent bit length) to optimize the balance between power consumption and output error. By systematically varying these parameters across different layers and data types, the patent achieves reduced power consumption while maintaining acceptable accuracy levels.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies different fixed point number formats to different layers and data types within the DNN, rather than using a uniform format. This local optimization allows each layer to use the most appropriate precision level for its specific computational requirements, minimizing overall error while reducing power consumption.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If fixed point number formats with reduced mantissa bit lengths are used, then silicon area is reduced, but output error increases

Engineering Contradiction:
Improvesilicon areaVSAvoidoutput error
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent optimizes the bit length parameters of fixed point number formats to reduce silicon area occupation. By reducing mantissa bit length and adjusting exponent bit length appropriately, the patent achieves compact hardware implementation while controlling output error through hierarchical optimization.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Different fixed point formats are assigned to different layers based on their specific computational characteristics. This localized format selection allows critical layers to maintain higher precision while less critical layers use reduced precision formats, optimizing the overall silicon area utilization.

Inventive Principle:
Principle #3Local quality

3Device complexity

If uniform fixed point number formats are used across all layers, then hardware implementation is simplified, but resource efficiency is reduced

Engineering Contradiction:
Improvehardware implementation complexityVSAvoidresource efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the DNN into different layers and data types, assigning optimized fixed point formats to each segment. This segmentation enables resource-efficient processing by matching computational requirements with appropriate precision levels, while the hierarchical optimization method keeps the overall system manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent develops a universal hierarchical optimization framework that can be applied to various DNN architectures and configurations. This framework provides a systematic approach to determining optimal fixed point formats across different layers, achieving resource efficiency without requiring completely custom hardware design for each layer.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260044707A1Hierarchical Mantissa Bit Length Selection For Hardware Implementation Of Deep Neural Network
Publication Date: 2026.02.12 IMAGINATION TECH LTD
  • US20260044707A1 patent drawing
  • US20260044707A1 patent drawing
  • US20260044707A1 patent drawing

AI summary

Hierarchical methods for selecting fixed point number formats with reduced mantissa bit lengths for representing values input to, and/or output, from, the layers of a DNN. The methods begin with one or more initial fixed point number formats for each layer. The layers are divided into subsets of layers and the mantissa bit lengths of the fixed point number formats are iteratively reduced from the initial fixed point number formats on a per subset basis. If a reduction causes the output error of the DNN to exceed an error threshold, then the reduction is discarded, and no more reductions are made to the layers of the subset. Otherwise a further reduction is made to the fixed point number formats for the layers in that subset. Once no further reductions can be made to any of the subsets the method is repeated for continually increasing numbers of subsets until a predetermined number of layers per subset is achieved.