DNN Layer Mantissa Bit Selection for Low-Power Hardware

The patent applies parameter changes by systematically varying the mantissa bit length parameter across different DNN layers. The method iteratively adjusts the mantissa bit length from an initial value downward, evaluating the impact on output accuracy at each step, and selects the maximum reduction that maintains accuracy within the threshold. This parameter optimization approach resolves the contradiction by finding the optimal balance between reduced bit length (lower power consumption) and maintained accuracy.

The patent applies local quality by assigning different mantissa bit lengths to different DNN layers based on their specific requirements. Rather than using a uniform format across all layers, the method determines the optimal mantissa bit length for each layer individually through iterative evaluation, allowing layers that can tolerate lower precision to use fewer bits while maintaining overall accuracy. This resolves the contradiction by optimizing resource efficiency locally in each layer while maintaining acceptable global performance.

The patent applies segmentation by dividing the DNN layers into multiple subsets and performing iterative mantissa bit length reduction on each subset separately rather than all layers simultaneously. The method processes subsets sequentially, evaluating accuracy impact and determining optimal bit lengths for each subset independently. This segmentation approach reduces the computational burden and time required compared to evaluating all layers together, while still achieving overall resource optimization.