DNN Register File Layout With Clock Gating and Gray-Coded Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DNN accelerators face significant power dissipation due to inefficient dynamic register files, which are a substantial source of power consumption and area inefficiency, particularly in resource-constrained edge devices, where reducing data movement and register file power is crucial for meeting latency and energy constraints.
Innovation Solution
Implementing power-efficient register files with integrated clock gating (ICG) units, flip-flops, and multiplexers using gray coding to reduce spurious transitions and data transitions, along with bit packing to minimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic register files are used in DNN accelerators, then data storage and access functionality is provided, but power consumption increases significantly
Solution Approach 1:
The patent changes the operational parameters of register files by implementing clock gating mechanisms that control clock signal distribution dynamically. The clock tree structure with gating units adjusts clock frequency and activation states based on actual register usage patterns, reducing power consumption while maintaining required functionality. This parameter change transforms the always-on register file into a selectively activated system.
Solution Approach 2:
The register file system is segmented into multiple independently controllable blocks, each with its own clock gating control. This segmentation allows different regions of the register file to be activated or deactivated based on specific computational needs, rather than activating the entire register file system. The patent divides the clock distribution network into hierarchical segments that can be controlled granularly.
2Quantity of substance
If register file size is increased to store more data, then data storage capacity improves, but area requirements increase
Solution Approach 1:
The patent implements a hierarchical nesting structure where multiple levels of multiplexers are nested within the register file architecture. Data can be stored more compactly by multiplexing multiple data paths through shared register resources. The nested multiplexer structure allows efficient data routing and storage, increasing effective storage capacity without proportional area increase.
Solution Approach 2:
Register files are designed with multi-functional capabilities where the same physical storage resources serve multiple purposes: storing activation data, weight data, and intermediate computation results. The universal register file structure can be dynamically reconfigured through the clock gating and multiplexing system to serve different data storage needs, increasing effective storage capacity without requiring dedicated storage areas for each function.
3Reliability
If clock signals are distributed to all register files continuously, then register operation reliability is maintained, but power consumption increases
Solution Approach 1:
Instead of continuous clock signal distribution, the patent implements periodic clock activation controlled by gating units. The clock signal is distributed only during periods when registers are actually needed for computation, with gating units selectively enabling or disabling clock distribution based on operational requirements. This periodic action maintains register reliability when needed while eliminating unnecessary clock power consumption during idle periods.
Solution Approach 2:
The harmful element of continuous clock distribution is extracted and removed through clock gating mechanisms. The gating units act as switches that extract and eliminate unnecessary clock signals from inactive register regions, allowing only essential clock distributions to proceed. This extraction approach maintains reliability for active registers while removing the power-wasting continuous distribution to inactive regions.
4Use of energy by moving object
If data transitions are reduced in register files, then power consumption decreases, but data access efficiency may be affected
Solution Approach 1:
The patent implements preliminary data positioning and pre-charging mechanisms that prepare data in optimal locations before actual access operations. By anticipating data access patterns and pre-positioning data or pre-charging signal paths, the system reduces the number of transitions required during actual data access, lowering power consumption without compromising access efficiency. The clock gating system also pre-activates necessary register regions before data operations begin.
Data Source
AI summary
A memory array of a compute tile may store activations or weights of a DNN. The memory array may include databanks for storing contexts, context MUXs, and byte MUXs. A databank may store a context with flip-flop arrays, each of which includes a sequence of flip-flops. A logic gate and an ICG unit may gate flip-flops and control whether states of the flip-flops can be changed. The data gating can prevent a context not selected for the databank from inadvertently toggling and wasting power A context MUX may read a context from different flip-flop arrays in a databank based on gray-coded addresses. A byte MUX can combine bits from different bytes in a context read by the context MUX. The memory array may be implemented with bit packing to reduce distance between the context MUX and byte MUX to reduce lengths of wires connecting the context MUXs and byte MUXs.