Compact 3-Way Doherty Amplifier Assembly Using Dual Semiconductor Dies
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Solution Overview
Problem
Fabricating 3 or more way Doherty amplifiers in a space-efficient manner is difficult, particularly for small cell applications where size is a critical requirement, despite their efficiency advantages in mobile base stations.
Innovation Solution
The amplifier arrangement utilizes two semiconductor dies within a dual path package, with a 3-way or 4-way Doherty amplifier configuration, where one die includes a main amplifier and one peak amplifier, and the other die includes the remaining peak amplifiers, along with Doherty splitter and combiner elements for signal splitting and combining, and bond wires forming inductance for impedance inversion, enabling compact integration and efficient signal handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If 3 or more way Doherty amplifiers are fabricated using conventional methods, then the amplifier functionality is achieved, but the device size becomes large and space efficiency is poor
Solution Approach 1:
The amplifier assembly is segmented into multiple semiconductor dies, with each die containing specific amplifier stages (main amplifier and peak amplifiers). This segmentation allows parallel fabrication of smaller, manageable units that can be independently manufactured with standard processes, then integrated into a compact multi-way Doherty amplifier configuration.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by placing multiple semiconductor dies in vertical layers within a single package. This vertical arrangement dramatically reduces the footprint area while maintaining all necessary amplifier functions, achieving space-efficient design without compromising fabrication ease.
2Area of stationary object
If multiple amplifiers are integrated in a single semiconductor device, then space efficiency is improved, but the device complexity and fabrication difficulty increase
Solution Approach 1:
The complex multi-way Doherty amplifier is divided into separate semiconductor dies, each handling specific amplifier stages. This segmentation reduces the complexity of individual fabrication processes while achieving high integration density through vertical stacking, thereby reducing package footprint without overwhelming fabrication capabilities.
Solution Approach 2:
Multiple semiconductor dies are nested vertically within a single package structure, with each die containing amplifier stages. This nested arrangement maximizes the use of three-dimensional space, reducing the horizontal footprint area while maintaining manageable complexity through modular die design and standard integration processes.
3Volume of moving object
If discrete power transistors are used for peak stages, then manufacturing flexibility is maintained, but the overall device size increases
Solution Approach 1:
The patent merges discrete power transistor peak stages with integrated main amplifier stages into a unified multi-die semiconductor structure. This combination maintains the manufacturing flexibility of discrete transistor design while achieving compact volume through vertical integration, eliminating the need for separate discrete component mounting and reducing overall assembly size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a compact and efficient 3-way or 4-way Doherty amplifier assembly, facilitating easier handling and impedance matching, while maintaining high efficiency parameters, particularly beneficial for small cell applications where space is limited.
Implementation Method 1
bond wires forming inductance for impedance inversion
Data Source
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Figure 5~6
AI summary
An amplifier assembly (100) comprising a three or more way Doherty amplifier arrangement mounted within a dual path package (101) having two RF input leads (107,108) and two RF output leads (112, 113), comprising a first semiconductor die (114) and a second semiconductor die (115), the first semiconductor die (114) having thereon two of at least three amplifiers and the second semiconductor die (115) having thereon up to two of the remaining amplifier or amplifiers of the at least three amplifiers; wherein the first semiconductor die (114) includes a Doherty splitter element configured to split an RF input signal received from the first RF input lead (107) to provide an input signal to the two amplifiers thereon and a Doherty combiner element to combine an output signal from the two amplifiers thereon, the Doherty combiner element connected to the first RF output lead (112); and wherein the amplifier or amplifiers of the second semiconductor die (115) are connected to the second RF input lead (108) and to the second RF output lead (113).