Doherty Amplifier GaN Die Area Reduction
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Solution Overview
Problem
High-efficiency power amplifier design for 5G wireless communication systems faces challenges in reducing physical die area and cost due to the high expense and lattice mismatch limitations of gallium-nitride (GaN) technology, which restricts wafer size and yields fewer power transistor dies compared to silicon-based semiconductors.
Innovation Solution
The implementation of Doherty power amplifier circuits with power transistor dies featuring reduced source-to-drain pitch, achieved by optimizing the arrangement of source vias, allowing for a smaller physical size while maintaining equivalent RF performance and thermal dissipation characteristics, thereby reducing the overall die area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If GaN technology is used for power amplifier design, then efficiency and output power are improved, but manufacturing cost and device area increase
Solution Approach 1:
The patent applies local quality by implementing different source-to-drain pitch values in different regions of the power transistor die. Specifically, a first region has a first source-to-drain pitch while a second region has a second source-to-drain pitch that is smaller than the first. This allows optimization of specific areas for different functions - maintaining adequate spacing where needed while reducing overall die area, thereby reducing manufacturing cost while preserving the high efficiency benefits of GaN technology
2Loss of energy
If GaN technology is used for power amplifier design, then efficiency and output power are improved, but physical die area increases
Solution Approach 1:
The patent implements local quality by creating regions with different source-to-drain pitch values within the power transistor die. The first region maintains a larger first source-to-drain pitch for optimal performance, while the second region uses a smaller second source-to-drain pitch to reduce overall die area. This spatial variation in geometric parameters allows the device to achieve high efficiency comparable to conventional GaN designs while occupying significantly less physical area
Solution Approach 2:
The patent applies parameter changes by varying the source-to-drain pitch parameter across different regions of the power transistor die. By changing this critical geometric parameter from a uniform value to a spatially varying value (first source-to-drain pitch in one region, second source-to-drain pitch in another region), the design achieves reduced die area while maintaining the efficiency characteristics of GaN technology
3Ease of manufacture
If conventional power transistor layout is used, then manufacturing is simplified, but thermal dissipation performance deteriorates
Solution Approach 1:
The patent applies local quality by implementing different source-to-drain pitch values in different regions of the power transistor die. Specifically, a first region has a first source-to-drain pitch while a second region has a second source-to-drain pitch that is smaller than the first. This allows optimization of specific areas for different functions - maintaining adequate spacing where needed while reducing overall die area, thereby reducing manufacturing cost while preserving the high efficiency benefits of GaN technology
Data Source
AI summary
Power amplifiers such as multi-path power amplifiers, systems employing such amplifiers, and methods of implementing amplifiers and amplifier systems are disclosed herein. In one example embodiment, a multi-path power amplifier includes a first semiconductor die with an integrated first transistor having a first source-to-drain pitch, and a second semiconductor die with an integrated second transistor having a second source-to-drain pitch, where the second source-to-drain pitch is smaller than the first source-to-drain pitch by at least 30 percent. In another example embodiment, a Doherty amplifier system includes a first semiconductor die with a first physical die area to total gate periphery ratio, and a second semiconductor die with a second physical die area to total gate periphery ratio, where the second physical die area to total gate periphery ratio is smaller than the first physical die area to total gate periphery ratio by at least 30 percent.