Doherty Amplifier Output Matching with Integrated Passive Devices

The patent applies asymmetry by using different transistor sizes for carrier and peaking power amplifiers. The peaking amplifier uses a larger transistor (e.g., 2x or 4x the size of the carrier amplifier transistor) to create current-carrying capacity differences. This asymmetric configuration enables load modulation greater than 2:1 VSWR, which improves back-off efficiency while the overall amplifier maintains linear operation through proper signal splitting and combining.

The patent merges discrete matching network components (inductors, capacitors) directly onto the semiconductor die, integrating them with the power amplifier transistors. This integration eliminates the need for separate discrete components and their associated parasitic inductances and capacitances. The matching networks are formed using on-chip metal layers and dielectric structures, achieving both compactness and reduced parasitic effects while maintaining design flexibility through standard semiconductor fabrication processes.

The patent implements nesting by placing the matching network components directly within and around the transistor structures on the same die. The inductors are formed using spiral patterns in metal layers, capacitors are created using stacked plate structures in dielectric layers, and these are nested within the overall amplifier layout. This nested integration achieves compact device footprint while maintaining ease of manufacture through standard semiconductor fabrication processes that can simultaneously create transistors and passive components.