Doherty Amplifier Path-Length Tuning for Phase-Aligned Combining

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In Doherty amplifier circuits, phase differences between signals at the combining node lead to deteriorated characteristics such as gain.

Innovation Solution

The Doherty amplifier circuit includes a division node that splits the input signal into multiple paths, each amplified by a GaN HEMT-based main amplifier and peak amplifiers. The electrical lengths of these paths are carefully adjusted to minimize phase differences at the combination node, thereby improving circuit characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrical lengths of signal paths in a Doherty amplifier circuit are not optimized, then the circuit structure is simpler, but phase differences between signals at the combining node deteriorate gain characteristics

Engineering Contradiction:
Improvegain characteristicsVSAvoidelectrical length optimization
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by optimizing the electrical lengths of transmission lines in the signal paths. Specifically, it sets the electrical length from the signal source to the main amplifier (L1) and from the main amplifier to the combining node (L2) to specific values that minimize phase differences between parallel signal paths. This parameter optimization resolves the contradiction by achieving better gain characteristics through precise electrical length control without adding complex phase adjustment circuits.

Inventive Principle:
Principle #35Parameter changes

2Power

If multiple parallel signal paths are used in a Doherty amplifier circuit, then signal amplification capability is improved, but phase differences between paths deteriorate overall circuit performance

Engineering Contradiction:
Improvesignal amplification capabilityVSAvoidoverall circuit performance
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent applies asymmetry by recognizing that different parallel signal paths have different electrical lengths and phase characteristics. Instead of making all paths identical, it asymmetrically optimizes each path's electrical length (L1, L2, L3, L4) to compensate for inherent differences. This allows multiple paths to contribute effectively to signal amplification while maintaining proper phase relationships at the combining node, thus improving power capability without sacrificing reliability.

Inventive Principle:
Principle #4Asymmetry

3Reliability

If electrical lengths between components are increased to reduce phase differences, then gain characteristics improve, but signal transmission time increases

Engineering Contradiction:
Improvegain characteristicsVSAvoidsignal transmission time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent optimizes the parameters of electrical length to achieve the best compromise between gain characteristics and signal transmission time. By calculating and setting specific electrical length values for transmission lines in parallel paths, it minimizes phase differences without unnecessarily increasing transmission time. This parameter optimization resolves the contradiction by finding the optimal electrical length values that improve gain while keeping transmission delays acceptable.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250183850A1Doherty amplifier circuit
Publication Date: 2025.06.05 SUMITOMO ELECTRIC DEVICE INNOVATIONS
  • US20250183850A1 patent drawing
  • US20250183850A1 patent drawing
  • US20250183850A1 patent drawing

AI summary

A Doherty amplifier circuit includes a division node that divides an input signal into first and second signals, a main amplifier that amplifies the first signal and outputs an amplified first signal as a third signal, a first peak amplifier that amplifies the second signal, and outputs an amplified second signal as a fourth signal, and a combination node that combines the third signal and the fourth signal and outputs a combined signal to an output terminal as an output signal, wherein a first electrical length of a sum of an electrical length between the division node and the main amplifier and an electrical length between the main amplifier and the combination node is shorter than a second electrical length of a sum of an electrical length between the division node and the first peak amplifier and an electrical length between the first peak amplifier and the combination node.