Multi-Stage Doherty Power Amplifier With SiGe-GaN Impedance Matching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Gallium nitride (GaN) power transistors face challenges in high-power amplifier circuits due to their high cost, complex digital pre-distortion linearization requirements, and mismatched input impedance, which limits efficiency and bandwidth in conventional amplifier topologies.

Innovation Solution

A multiple-stage amplifier design incorporating a SiGe driver stage IC die electrically coupled to a GaN final stage IC die in a cascade arrangement, where the SiGe driver stage functions as a pre-match impedance conditioner and gain enhancer for the GaN final stage, enabling improved linearity and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If GaN transistors are used in high-power amplifier circuits, then power density and unit current gain frequency are improved, but cost increases significantly

Engineering Contradiction:
Improvepower densityVSAvoidcost
Core Design Contradiction:
PowerVSEase of manufacture

Solution Approach 1:

The amplifier is divided into multiple stages with different transistor technologies: early stages use lower-cost silicon-based transistors while later stages use GaN transistors for high power output. This segmentation allows the system to achieve high power density where needed while controlling overall cost by using cheaper technologies where sufficient performance is adequate.

Inventive Principle:
Principle #1Segmentation

2Power

If GaN transistors are used in Doherty power amplifier, then power density is improved, but input impedance mismatch worsens

Engineering Contradiction:
Improvepower densityVSAvoidinput impedance match
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

An impedance matching network is introduced as an intermediary component between the 50 Ohm gain stage and the GaN peaking amplifier. This matching network transforms the impedance to accommodate GaN's low input impedance characteristics, reducing reflections and improving input return loss while preserving the power density benefits of GaN transistors.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The input impedance parameters of the amplifier stage are changed and optimized specifically for GaN transistor operation. By adjusting impedance parameters and using appropriate matching networks, the system adapts to GaN's inherent low input impedance and high Q-factor characteristics, converting what would be a mismatch into an optimized operating condition.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If GaN peaking amplifier transitions between off and on states, then power efficiency is improved, but input impedance variation increases

Engineering Contradiction:
Improvepower efficiencyVSAvoidinput impedance stability
Core Design Contradiction:
Loss of energyVSStability of the object's composition

Solution Approach 1:

The amplifier employs dynamic impedance matching that adapts as the GaN peaking amplifier transitions between off and on states. The matching network is designed to handle the dynamic impedance variations that occur during state transitions, maintaining acceptable input match across different operating conditions while preserving the power efficiency benefits of the GaN transistor's ability to switch states.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12224713B2Multiple-stage Doherty power amplifiers implemented with multiple semiconductor technologies
Publication Date: 2025.02.11 NXP USA INC
  • US12224713B2 patent drawing
  • US12224713B2 patent drawing
  • US12224713B2 patent drawing

AI summary

A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.