Doherty PA Balun Stacking to Cut EMI and Footprint

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Solution Overview

Problem

The existing power amplification devices using differential Doherty circuits face characteristic degradation due to electromagnetic interference between the carrier balun and the peak balun, leading to increased device size as they are disposed apart to mitigate this issue.

Innovation Solution

The power amplification device is designed with the carrier balun and peak balun arranged on different insulating layers within the substrate, allowing them to be positioned closer together without significant electromagnetic interference, and utilizing the dead space between them for additional components like a surface mount device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If the carrier balun and peak balun are disposed apart from each other by a predetermined distance to reduce electromagnetic interference, then the electromagnetic interference is reduced, but the size of the power amplification device increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoiddevice size
Core Design Contradiction:
Object-affected harmful factorsVSArea of stationary object

Solution Approach 1:

The patent applies three-dimensional stacking of insulating layers to resolve the spatial conflict between carrier balun and peak balun. By placing these components on different insulating layers (different z-dimension) rather than separating them on the same layer (x-y dimension), the patent eliminates electromagnetic interference while maintaining a compact footprint. The vertical stacking enables components to occupy different spatial dimensions, effectively reducing device area without compromising interference mitigation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nesting by placing the carrier balun and peak balun within a hierarchical structure of multiple insulating layers. The components are nested in the vertical dimension, with each balun residing on a specific insulating layer that is stacked above or below the other. This nested arrangement allows tight spatial integration while maintaining electrical isolation, thereby reducing overall device area without increasing electromagnetic interference.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If the carrier balun and peak balun are disposed close to each other to reduce device size, then the device size is reduced, but electromagnetic interference increases causing characteristic degradation

Engineering Contradiction:
Improvedevice sizeVSAvoidelectromagnetic interference
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent transitions from two-dimensional planar separation to three-dimensional vertical stacking. By utilizing the stacking direction (z-axis) through multiple insulating layers, the patent allows carrier balun and peak balun to be positioned close in the x-y plane while maintaining spatial separation in the z-axis. This dimensional transition enables compact device layout without sacrificing electromagnetic isolation.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces insulating layers as intermediary structures between the carrier balun and peak balun. These insulating layers act as mediators that provide electrical isolation and reduce electromagnetic coupling while allowing the baluns to be positioned in close proximity. The intermediary insulating layers enable tight integration without direct electromagnetic interaction between the baluns.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If dead space between carrier balun and peak balun is utilized for additional components, then device functionality is enhanced, but the layout complexity increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidlayout complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent utilizes the vertical dimension created by stacked insulating layers to accommodate additional components. Instead of competing for horizontal space, components can be distributed across different z-levels (insulating layers). This vertical distribution strategy enhances device functionality by allowing more components to coexist without significantly increasing horizontal footprint or layout complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the device layout into distinct insulating layers, each potentially hosting different components. This segmentation allows independent placement and routing on each layer, reducing overall layout complexity. By dividing the spatial domain into discrete layers, the patent enables systematic component distribution and simplifies the organization of complex multi-component layouts.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250047244A1Power amplification device
Publication Date: 2025.02.06 MURATA MFG CO LTD
  • US20250047244A1 patent drawing
  • US20250047244A1 patent drawing
  • US20250047244A1 patent drawing

AI summary

A power amplification device that includes a substrate having a surface; an integrated circuit including a carrier amplifier and a peak amplifier and disposed on the surface; a carrier balun connected to the carrier amplifier; a peak balun connected to the peak amplifier; and a surface mount device disposed on the surface. Each of the carrier amplifier and the peak amplifier is a pair of differential amplifiers. The substrate includes multiple insulating layers arranged in a stacking direction. An electrode to which the surface mount device is soldered is provided on the surface. In a view from the stacking direction, the carrier balun, the electrode, and the peak balun, which are arranged in a second planar direction, are disposed on one side of the integrated circuit in a first planar direction.